Digital-analog hybrid mode clock duty ratio calibration circuit

Abstract

The invention discloses a digital-analog hybrid mode clock duty ratio calibration circuit which is characterized by comprising a pulse generator (1), a half-period delay line (2), a RS trigger (3), a single end-to-difference switching circuit (4), a digital-analog hybrid charge pump (5) and an error amplifier (6), wherein the input end of the pulse generator (1) is connected with an original input clock signal (CKI) to be calibrated; and the output end signal of the pulse generator (1) is a buffered input clock pulse signal (CKB), and the signal is simultaneously connected to the clock input end of the half-period delay line (2) and the setting input end (S) of the RS trigger (3). The digital-analog hybrid mode clock duty ratio calibration circuit disclosed by the invention overcomes the discrete type existing in the adjustment of the traditional pure digital mode duty ratio calibration circuit, realizes the continuous duty ratio adjustment, adopts fully-digital processes, and obtains higher adjustment accuracy under the condition of consuming small area and power consumption.

Description

technical field [0001] The invention is applicable to the application occasions of clock duty ratio calibration in various high-speed communication transmissions, such as high-speed data memory, pipeline processor, etc., and belongs to the technical field of duty ratio calibration circuit design. Background technique [0002] With the continuous improvement of integrated circuit technology, the working speed of chips has been continuously improved, and technologies such as double data rate (Double Data Rate, DDR) and pipeline (Pipeline) have been widely used to obtain greater data throughput. More stringent timing accuracy is required, which means that the performance requirements of the system clock are also higher, and one of the important performance indicators is the duty cycle of the clock. A clock with a 50% duty cycle is most beneficial for data propagation, and for a system that adopts a double data rate and pipeline operation mode, a 50% duty cycle can ensure that t...

AI Technical Summary

Problems solved by technology

However, because the digital method is limited by the minimum delay unit, the calibration accuracy is discrete, and it is often impossible to obtain accurate calibration results.

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