Graphene device and production method thereof

Abstract

The invention discloses a graphene device and a production method thereof. A gate region provided with a metal gate is formed on a graphene substrate and contact plug structures containing nanoscale catalyst metal grains and carbon nano-tubes on the nanoscale catalyst metal grains are formed on graphene at two sides of the gate region; the nanoscale catalyst metal grains not only have the function of inducing the carbon nano-tubes to grow, but also have the function of adjusting barrier height when the carbon nano-tubes contact the graphene, so that the contact resistance of the graphene device is reduced; and since the carbon nano-tubes have high conductivity, the bulk resistance of a contact plug is greatly reduced, and further the parasitic resistance of the graphene device is reduced and the performance of the device is improved.

Description

technical field [0001] The present invention generally relates to a semiconductor device and a manufacturing method thereof, in particular to a graphene semiconductor device and a manufacturing method thereof. Background technique [0002] At present, for forward-looking pilot research, the international community is most concerned about whether CMOS devices can still be based on silicon semiconductor substrates after the 11nm-16nm technology generation. A research hotspot is to develop new material systems with higher carrier mobility and new technical means to further extend Moore's Law and surpass Si-CMOS (Beyond Si-CMOS), and promote the development of integrated circuit technology. [0003] Graphene material has attracted extensive attention due to its excellent physical properties, and it is a very promising carbon-based material. Graphene is a monoatomic layer of graphite crystal film, and its lattice is a hexagonal lattice honeycomb two-dimensional structure compose...

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Problems solved by technology

Among them, due to the ultra-thin characteristics of the graphene substrate (single-layer or multi-layer structure), the method of using ion implantation to form the PN junction source / drain region in the traditional CMOS process is no longer applicable, but adopts the method of forming the PN junction source / drain region on both sides of the gate region. The method of directly growing metal electrodes on the graphene substrate, but the problem brought about by this is the relatively high parasitic resistance, which will affect the speed and performance of the device

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