Planarization method for back gate process and device structure thereof

A planarization method and gate-last process technology, which are applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problem of difficulty in controlling gate height in gate-last process, and achieve precise control of height, reduction of resistance, and filling. The effect of increasing the space

Inactive Publication Date: 2012-03-21
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The purpose of the present invention is to at least solve one of the above-mentioned technical problems, especially by proposing a planarization method for the gate-last process to solve the problem that the height of the gate is difficult to control in the gate-last process

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  • Planarization method for back gate process and device structure thereof
  • Planarization method for back gate process and device structure thereof
  • Planarization method for back gate process and device structure thereof

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Embodiment Construction

[0018] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings, in which the same or similar reference numerals indicate the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary, and are only used to explain the present invention, and cannot be construed as limiting the present invention.

[0019] The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are only examples, and are not intended to limit the invention. In addition, the present invention may repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplificat...

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Abstract

The invention provides a planarization method for a back gate process of an MOS (metal oxide semiconductor) device and a structure thereof. In the back gate process of the MOS device, a CMP (chemical mechanical planarization) process is utilized for planarization of an interlay dielectric layer, and an etching technology is utilized to remove a hard masking layer on a false gate stacking layer, so that the purpose of accurately controlling the heights of a false gate and a metal gate is achieved. In addition, the MOS device forms T-shaped stacking of the gates, and the length of the gate at the upper part is more than that of the gate at the lower part, so that the filling space of the metal gate material in a gate groove is enlarged so as to be beneficial to reducing the resistance of the metal gate.

Description

Technical field [0001] The present invention relates to the field of semiconductor design and manufacturing, in particular to a planarization method used in a gate last process and a device structure thereof. Background technique [0002] With the reduction of the size of semiconductor devices, especially in the 22nm and below technology generation, MOS device gate engineering research with high-k gate dielectric / metal gate technology as the core is the most representative core process. At present, research on high-k gate dielectric / metal gate technology can be divided into front gate process (Gate first) and replacement gate or gate last process (Replacement gate or Gate last). A significant advantage of the gate last process is that the gate does not require Withstand high annealing temperatures. [0003] In the gate last process, the planarization of the gate structure is one of the indispensable steps, and the prior art is usually implemented by chemical mechanical polishing (...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/423H01L21/304H01L21/311H01L21/28
Inventor 王文武赵超李俊峰
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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