Layout structure of power metal oxide semi-field effect transistor (power MOSFET)

Abstract

The invention discloses a layout structure of a power metal oxide semi-field effect transistor (power MOSFET). The layout structure comprises a first sinuous grid structure, a first contact structure and a second contact structure, wherein the first sinuous grid structure is arranged in a substrate and provided with a first edge and a second edge; the first contact structure is arranged in the substrate and positioned at the first edge of the first sinuous grid structure; and the second contact structure is arranged in the substrate and positioned at the second edge of the first sinuous grid structure.

Description

technical field [0001] A layout structure of a power metal oxide field effect transistor (Power MOSFET), especially a layout structure that can increase the channel width of a power transistor in the same area by means of a layout of a gate structure. Background technique [0002] When designing voltage conversion circuits such as power converters (DC-DC), low dropout (LDO) regulators, switching regulators (switching regulators) and chargers (chargers), the power metal oxide semiconductors used Considering the characteristics of dropout voltage (dropout voltage), drain-to-source resistance (Rdson) and output current (output current), a field effect transistor (Power MOSFET) needs to be realized with a larger size. [0003] refer to Figure 1A , Figure 1A It is a schematic diagram of the layout of a conventional power MOSFET. The power MOSFET 1 has a strip-shaped gate structure 14 located on a substrate 100 . In the substrate 100 on both sides of the gate structure 14 , on...

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Problems solved by technology

However, the layout area required by this layout method is relatively large, resulting in poor integration of the traditional power MOSFET layout and increased manufacturing costs.

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