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LDPC (low density parity check) decoder and decoding method based on layer decoding processing

A decoder and decoding technology, which are applied in the field of LDPC decoders and decoding based on layer decoding processing, can solve problems such as difficulty in generalization, consumption of hardware resources and interconnection complexity, and improve throughput, meet the needs of High-speed data processing requirements, the effect of reducing the clock cycle

Inactive Publication Date: 2012-03-28
BEIJING UNIV OF POSTS & TELECOMM
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] The technical problem to be solved by the present invention is: how to solve the problems of high consumption of hardware resources, high interconnection complexity and difficulty in general use in conventional LDPC decoders

Method used

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  • LDPC (low density parity check) decoder and decoding method based on layer decoding processing
  • LDPC (low density parity check) decoder and decoding method based on layer decoding processing
  • LDPC (low density parity check) decoder and decoding method based on layer decoding processing

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Embodiment 1

[0087] This embodiment is used figure 2 Shown H 0 The decoding of the 1 / 2 rate LDPC code corresponding to. Such as Figure 4 As shown, the decoder in this embodiment includes the following parts:

[0088] The node update processing unit CNPU set includes a total of node update processing units, which are 40_1,...40_x, 40_a. In this embodiment, the check matrix H 0 Number of row blocks q 0 Is 12, the number of columns p 0 It is 24, and the unit cyclic matrix size a is 96, so the number of CNPUs is equal to the unit cyclic matrix size a, and each CNPU corresponds to a row and column equation in the check matrix. CNPU completes the update operation of the check node information and variable node information corresponding to the Tanner graph in the iterative process; the check node update operation unit CNU set is 50, including a node update processing units, respectively 50_1, .. ....50_x, 50_a; check node storage unit, respectively 10_1,......10_x, 10_a; variable node storage uni...

Embodiment 2

[0123] This embodiment is used figure 2 Shown H 0 , H 1 , H 2 Decoding of LDPC codes of the corresponding mixed code rate. Where H 0 Is the check matrix corresponding to the code rate 1 / 2, H 1 Is the check matrix corresponding to the code rate of 2 / 3, H 2 It is a check matrix with a corresponding code rate of 3 / 4. Compared with Embodiment 1, the configuration process of addressing and offset parameter memory is different in this embodiment only in the initialization phase, which is described as follows: In this embodiment, the initialization configuration phase needs to be configured according to different code rates. Different control parameters. For different code rates, different parameter storage tables can be used, such as Table 1 for storing H 0 Corresponding control parameters, Table 2 is used to store H 1 Corresponding control parameters, Table 3 is used to store H 2 The corresponding control parameter. The storage mode of each storage table is still in the order of t...

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Abstract

The invention relates to the technical field of channel coding and discloses an LDPC (low density parity check) decoder based on layer decoding processing, which comprises a node updating processing unit, a variable node storage unit, a check node storage unit, an addressing and offset control ROM (read only memory) configuration group, a cyclic shifting network, an output buffer, an address signal controller, and a decoding time sequence controller, wherein the node updating processing unit is used for carrying out updating-operation on check node information and variable node information, the variable node storage unit is used for storing initialized information and updated variable node information, the check node storage unit is used for storing updated check node information, the addressing and offset control ROM configuration group is used for configuring various control signals, the cyclic shifting network is used for carrying out cyclic shifting on data read by variable nodes, the output buffer is used for storing judgment bits during decoding process, the address signal controller is used for addressing storage units used in LDPC decoder, and the decoding time sequence controller is used for fixing the sequence for the operation of the node updating processing unit, and controlling the data exchange among the node updating processing unit and the storage units. The invention can solve the problems that hardware in the common decoder is large in resource consumption, high in interconnection complex degree and not easy for universality.

Description

Technical field [0001] The present invention relates to the technical field of channel coding, in particular to an LDPC decoder and decoding method based on layer decoding processing. Background technique [0002] Since Shannon proposed the channel coding theorem, coding researchers have been working to find a achievable channel coding scheme with performance as close to the Shannon limit as possible, and with lower complexity. [0003] LDPC code (low-density parity check code) first appeared in the binary rule LDPC code proposed by Gallager in 1962. It can be regarded as a linear group with a sparse check matrix (the number of "1"s in the check matrix is ​​small) code. Its performance in AWGN (Additive White Gaussian Noise) channels is close to the Shannon limit and its implementation complexity is low. The LDPC code is a kind of linear block code. Its check matrix is ​​a sparse matrix, that is, except for a few elements in the matrix that are non-zero, most of the other element...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
Inventor 刘佳康桂霞张平朱莹
Owner BEIJING UNIV OF POSTS & TELECOMM
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