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5V PMOS (P-channel Metal Oxide Semiconductor) device in SONOS (Silicon Oxide Nitride Oxide Semiconductor) technique and fabrication method thereof

A device and process technology, applied in the manufacturing field of 5-volt PMOS devices and 5-volt PMOS devices, can solve the problems of weakening competitiveness, process complexity and process cost increase, and achieve test time reduction, test cost saving, and improved shock. The effect of breakdown voltage

Active Publication Date: 2013-09-11
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, if the method of introducing high-voltage technology or high-voltage devices is introduced, the complexity and cost of the process will increase a lot, and the competitiveness brought about by the improvement of product performance will also weaken.

Method used

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  • 5V PMOS (P-channel Metal Oxide Semiconductor) device in SONOS (Silicon Oxide Nitride Oxide Semiconductor) technique and fabrication method thereof
  • 5V PMOS (P-channel Metal Oxide Semiconductor) device in SONOS (Silicon Oxide Nitride Oxide Semiconductor) technique and fabrication method thereof
  • 5V PMOS (P-channel Metal Oxide Semiconductor) device in SONOS (Silicon Oxide Nitride Oxide Semiconductor) technique and fabrication method thereof

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Embodiment Construction

[0022] Such as image 3 Shown is a schematic structural diagram of a 5-volt PMOS device in a SONOS process according to an embodiment of the present invention. In the SONOS process of the embodiment of the present invention, a 5-volt PMOS device is formed on a silicon substrate 6, and the silicon substrate 6 is an N-type silicon substrate or an N well is formed on the silicon substrate; the active region is isolated by a shallow trench (STI) means shallow trench field oxygen 2 isolation. The PMOS devices include:

[0023] A gate structure formed on the active region, the gate structure includes a gate oxide layer 5 and a polysilicon gate 3 , and a gate sidewall 4 is also formed on the sidewall of the gate structure.

[0024] P-type source and drain regions 1 formed on both sides of the gate structure and in the active region, and formed at the bottom of the gate structure and in the active region between the P-type source and drain regions N-type channel region. Wherein, t...

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Abstract

The invention discloses a 5V PMOS (P-channel Metal Oxide Semiconductor) device in the SONOS (Silicon Oxide Nitride Oxide Semiconductor) technique, and the junction depth of the side of a P-type source-drain region of the PMOS device close to a shallow trench field oxide is greater than the junction depth of the side of the P-type source-drain region close to an N-type trench region. The invention also discloses a fabrication method for the 5V PMOS device in the SONOS technique. The invention can improve the topography of the source / drain PN junction of the PMOS device, thus increasing the breakdown voltage of the 5V PMOS device, and moreover, the invention can further increase the information-erasing and information-writing operation voltages of an SONOS flash memory, increase the operation speed, improve the performance of the SONOS flash memory, shorten the test time of the SONOS flash memory and save the test cost.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a 5-volt PMOS device in a SONOS process; the invention also relates to a manufacturing method for a 5-volt PMOS device in the SONOS process. Background technique [0002] At present, the existing SONOS flash memory has become one of the mainstream flash memory types due to its advantages of high density and large capacity, and is widely used in electronic products such as digital cameras and smart phones. One of the advantages of the existing SONOS flash memory in terms of circuit and process is that there is no need to provide high-voltage devices, and the highest operating voltage, that is, the voltage generally used for information erasing and writing, can be within 12 volts, compared with the floating gate FLASH flash memory. The maximum operating voltage is much lower. Therefore, one of the disadvantages of the existing SONOS process is that the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
Inventor 刘冬华钱文生董金珠
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP