Metal-insulator-metal (MIM) capacitor structure and manufacturing method thereof

Abstract

The invention provides a method for manufacturing a metal-insulator-metal capacitor structure. The method comprises the following steps of: providing a front-end device structure on which a first interlayer dielectric layer is formed; etching the first interlayer dielectric layer until the surface of the front-end device structure is exposed to form a groove in the first interlayer dielectric layer; sequentially forming a lower metal barrier layer, a capacitance dielectric layer and an upper metal barrier layer on the first interlayer dielectric layer and in the groove; and flattening the upper metal barrier layer to make the surface of the upper metal barrier layer flush with the surface of the first interlayer dielectric layer. By the method, problems caused by different depths of through holes which are required to be formed at the same time in various interconnect structures can be solved, such as damage to an upper plate electrode of an MIM capacitor.

Description

technical field [0001] The present invention relates to the field of semiconductor manufacturing, and in particular, to metal-insulator-metal (MIM) capacitors and methods of making the same. Background technique [0002] At present, capacitors in semiconductor devices can be roughly classified into polysilicon-insulator-polysilicon (PIP) capacitors and metal-insulator-metal (MIM) capacitors according to their structure. In practical applications, these capacitors can be selectively used according to the characteristics of semiconductor devices. For example, in high-frequency semiconductor devices, MIM capacitors can be used. [0003] With the improvement of the integration level of semiconductor devices, capacitors are required to have larger capacitance values ​​to ensure that the capacitors can work normally. However, the PIP capacitor suffers from a decrease in capacitance value due to oxidation easily occurring at the interface between polysilicon as upper / lower electr...

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Problems solved by technology

Therefore, a through hole etching process with a very high etching selectivity is required, otherwise the through hole 142a will easily penetrate the upper electrode plate and be connected to the capacitor dielectric layer 122, thereby making the MIM capacitor structure invalid

In addition, since the depths of the trenches (trench) 141b-143b in the copper interconnection structures 141-143 are only controlled by the main etching (ME), but the main etching cannot control the etching depth and the uniformity of the etching at the same time. , thus easily lead to poor uniformity of sheet resistance (square resistance)

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