Analog circuit test node selecting method based on dynamic feedback neural network modeling

A neural network modeling and testing node technology, applied in the field of analog circuit test node selection, can solve problems such as unreasonable fault fuzzy interval design, high dependence on test node selection criteria, etc., and achieve the effect of strong nonlinear mapping ability

Inactive Publication Date: 2012-06-27
NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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Problems solved by technology

[0006] The purpose of the present invention is to solve the shortcomings of unreasonable fault fuzzy interval design and high dependence on test node selection criteria in the existing iterative selection method for analog circuit test nodes, and propose an

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  • Analog circuit test node selecting method based on dynamic feedback neural network modeling
  • Analog circuit test node selecting method based on dynamic feedback neural network modeling
  • Analog circuit test node selecting method based on dynamic feedback neural network modeling

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Embodiment Construction

[0053] The technical scheme of the present invention is described in detail below in conjunction with accompanying drawing:

[0054] The analog circuit test node selection method based on dynamic feedback neural network modeling of the present invention, such as figure 1 shown, including the following steps:

[0055] Step A. Select the frequency of the test signal.

[0056] In order to select the frequency that can improve the fault diagnosability, the present invention selects the frequency on the amplitude-frequency response curve that can improve the fault diagnosability most, based on the amplitude-frequency response curve of the circuit to be tested, and taking the maximum interval of the fault class within a class as the selection basis. The inflection point frequency is used as the test frequency, as follows:

[0057] Step A1, obtaining the amplitude-frequency response curve of the circuit to be tested; for example, a simulation tool such as PSPICE can be used to simu...

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Abstract

The invention discloses an analog circuit test node selecting method based on dynamic feedback neural network modeling. The method comprises the steps of selecting the frequency of a test signal, inputting the test signal into a circuit to be tested, simulating various typical fault conditions, collecting the voltage values of a normal sample and a fault sample of the circuit on a test node to be selected of the circuit to be tested so as to construct a fault dictionary table; according to a fault fuzzy voltage interval, analyzing a fuzzy fault set and obtaining a fault integer encoding table; constructing an initial training sample set, training an initial dynamic feedback neural network, and utilizing the dynamic feedback neural network for fitting the nonlinear mapping relation between the test node and the fault; and according to the target function calculated by the genetic algorithm output by the network, obtaining the optimal test node set by utilizing the genetic optimization algorithm. In the method, a fault dictionary is analyzed by the intelligent algorithm, so that the global optimum test node set can be found, and the subsequent diagnostic accuracy can be further improved.

Description

technical field [0001] The invention relates to a method for selecting an analog circuit test node, in particular to a method for selecting an analog circuit test node based on dynamic feedback neural network modeling. Background technique [0002] As the scale of electronic equipment continues to increase and the degree of integration continues to rise, the testing and diagnosis requirements of analog electronic systems are getting higher and higher, and the testability analysis of circuits is particularly important as the first important step in the diagnosis and identification of analog circuit faults. , this is because: (1) Not every measuring point in the circuit to be tested is measurable. (2) Some measurable nodes are redundant. (3) The fault information extracted by good test nodes is more distinguishable. Therefore, for a circuit to be tested, a good set of test nodes can effectively improve the fault testability of the circuit and reduce the test time of the circ...

Claims

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Application Information

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IPC IPC(8): G01R31/316
Inventor 罗慧王友仁林华姜媛媛崔江
Owner NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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