Method for extracting parasitic parameters of interconnection lines and device

Abstract

The invention provides a method for extracting parasitic parameters of interconnection lines. The method includes obtaining the thickness of each interconnection line of each grid of a layout after the integrated circuit layout is divided into the grids in a parasitic parameter extraction process; extracting the parasitic parameters of the interconnection lines of the grids of the layout according to the obtained thicknesses of the interconnection lines so as to obtain parasitic parameter extraction results with consideration of thickness differences. Correspondingly, the invention further provides a device for extracting the parasitic parameters of the interconnection line. The thickness differences of the interconnection lines caused by CMP (chemical mechanical polishing) process are taken into consideration in the method, more accurate geometric information of the interconnection lines is adopted in the parasitic parameter extraction process, and accordingly more accurate parasitic parameters can be obtained.

Description

technical field [0001] The invention relates to the fields of integrated circuit manufacturing and electronic design automation, in particular to a method for extracting parasitic parameters of interconnection lines. Background technique [0002] In the manufacturing process of integrated circuits (Integrated Circuit, IC), metals, dielectrics and other materials are fabricated on the surface of silicon wafers by various methods such as physical vapor deposition and chemical vapor deposition to form electronic components and components. The metal structure layer of the metal interconnection line between each layer is connected with a plurality of metal-filled through holes, which makes the circuit have high complexity and circuit density. An important indicator of integrated circuit performance is path delay, that is, the time required from an input to an output. The path delay of an integrated circuit includes device delay and interconnect delay between devices. With the re...

AI Technical Summary

Problems solved by technology

The difference in the thickness of the interconnection line will lead to inaccurate extraction results using the parasitic parameter extraction tool of the interconnection line

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