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Computer hardware platform design method based on DSP (digital signal processor) and FPGA (field programmable gate array)

A computer hardware and design method technology, applied in the field of embedded computer hardware platform design, can solve the problems of insufficient computing speed of the platform, difficulty in reducing the volume and weight, and difficult precise control of peripherals, etc., to reduce software workload, peripheral communication circuits, etc. Effects of simplification and reduction of development costs

Active Publication Date: 2012-07-11
XIAN KEYWAY TECH +1
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  • Abstract
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  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The object of the present invention is to provide a kind of computer hardware platform design method based on DSP and FPGA, it is to solve the problem that existing platform calculation speed is not enough, it is difficult to realize precise control to peripherals and the volume and weight are large and difficult to meet the requirements

Method used

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  • Computer hardware platform design method based on DSP (digital signal processor) and FPGA (field programmable gate array)
  • Computer hardware platform design method based on DSP (digital signal processor) and FPGA (field programmable gate array)

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Embodiment Construction

[0033] This platform uses DSP and FPGA as the core, through the expansion program loading module, data storage module, analog input module, analog output module, switch input module, switch output module, serial communication module, 1553B communication module and reset Circuits and power circuits, etc., to achieve the acquisition of analog and switching values, to achieve large-capacity program and data storage, to achieve complex algorithms, to achieve communication and control with peripherals, etc.

[0034] The design block diagram of the present invention is as figure 1 Shown:

[0035](1) The program loading module is composed of the data line, address line and control line of the program memory FLASH in the figure and the interface circuit of the digital signal processor DSP respectively. FLASH is used to store user programs and setting values, and the capacity can be selected according to user needs, and the maximum can store 1Mword; (2) The data storage module is comp...

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Abstract

A computer hardware platform design method based on a DSP (digital signal processor) and an FPGA (field programmable gate array) includes the steps: utilizing the DSP and the FPGA as a core to expand a program load module, a data storage module, an analog input module, an analog output module, a switching value input module, a switching value output module, a serial port communication module, a 1553B communication module, a reset circuit and a power circuit, so that an embedded computer hardware platform is built; and acquiring the analog quantity and the switching value, realizing high-capacity program and data storage and a complicated algorithm, realizing communication of the embedded computer hardware platform with peripherals, and controlling the embedded computer hardware platform. By the aid of the method, automatic switching of analog signal input and output is realized, switching value signal input and output are freely expanded, operating efficiency of a processor is greatly improved, systematic resources are saved, development cycle is shortened, and development cost is reduced. Another novel hardware design platform can be completed only by changing codes of the FPGA.

Description

technical field [0001] The invention belongs to the field of embedded computer hardware platform design, in particular to a computer hardware platform design method based on DSP (digital signal processor) and FPGA (programmable logic device) as the core. Background technique [0002] TI's TMS320C6713 is a high-performance 32-bit floating-point high-performance digital signal processor (DSP). Integrates a 32×32bit multiplier. The internal memory of the chip adopts a two-level high-speed cache structure and an 8-level pipeline structure. The internal bus includes a 32-bit program address bus and a 256-bit program data bus. The external data bus is 32bit, the address bus is 20bit, the external address selection space CE0~CE3, there are 4 kinds of program loading methods and flexible EMIF expansion interface. Due to its excellent computing power, efficient instruction set, intelligent peripherals, large-capacity on-chip memory and wide-range addressing capability, it is especi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/76
Inventor 刘升何健
Owner XIAN KEYWAY TECH
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