Processing method for power down and abnormal writing of solid state disc and system

A technology of solid-state hard disk and processing method, which is applied in the direction of data processing power supply, protection of stored content to prevent loss, etc., and can solve problems such as damage
CN102591807AActive Publication Date: 2012-07-18RAMAXEL TECH SHENZHEN

Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
RAMAXEL TECH SHENZHEN
Publication Date
2012-07-18

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Abstract

A processing method for power down and abnormal writing of a solid state disc comprises the steps of step 100, scanning a flash array, obtaining stored management information, performing initialization after extracting the management information, generating a plurality of mapping areas, dynamically adjusting the mapping areas, and managing the conversion between a multi level cell (MLC) to a single level cell (SLC); step 200, performing data reading and writing, during reading, finding a corresponding physical address through the two mapping areas, and reading the data on a flash memory; step 300, when the data is written, if finding a first mapping area already has no spare low level page, then starting waste page recovery management and abrasion balance management, after the abrasion balance management preferably recovers the waste page according to information in a mapping list of the first mapping area and then distributes the spare page, writing the data into the first mapping area; and step 400, when the conditions of power down or abnormal writing happen, enabling the plurality of mapping areas to perform corresponding operations to recover the data.
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Description

technical field

[0001] The invention relates to the field of solid-state hard disks, in particular to a method and system for handling power-off and writing exceptions of solid-state hard disks. Background technique

[0002] With the extensive application of MLC (multi level cell) NAND FLASH, the NAND FLASH used in solid-state hard disks is also mainly selected from MLC NAND FLASH. For most MLC NAND FLASH, it has remarkable characteristics: namely, as attached figure 1 , the two bits in the same unit are allocated in two different pages, that is, the upper page and the lower page, so that there is a strong coupling between the two pages. The write operation will have two phases: low page write (1 st round) and upper page writes (2 nd round), if the high-order page write operation is abnormal, the data in the low-order page will also be destroyed. On the contrary, if the low-order page write operation is abnormal, it will not affect the high-order page.

[0003] At pres...

Claims

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