Storage unit and single-end low-swing bit line writing circuit

Abstract

The invention relates to a storage structure and a single-end low-swing bit line writing circuit. The circuit comprises at least one storage unit and a driving circuit, wherein the driving circuit comprises a first phase inverter (I1), and the input end of the first phase inverter (I1) is used for writing data (D). The circuit is characterized in that the driving circuit also comprises a first P-channel metal oxide semiconductor (PMOS) transistor (P1), a second PMOS transistor (P2), a first N-channel metal oxide semiconductor (NMOS) transistor (N1) and a second NMOS transistor (N2), the writing circuit also comprises a feedback control circuit, the storage unit comprises a third PMOS transistor (P3), a fourth PMOS transistor (P4), a third NMOS transistor (N3), a fourth NMOS transistor (N4), a fifth NMOS transistor (N5) and a sixth NOMS transistor (N6). The assistance of additional reference voltage or power supply voltage is not needed for realizing the low-swing technology, and in addition, the single-end single-swing writing is supported through the improved storage unit.

Description

technical field [0001] The invention relates to a writing circuit for on-chip memory, in particular to a storage unit and a single-end low swing bit line writing circuit. Background technique [0002] In the design of multi-port static memory or register file, a single-ended structure is generally used to achieve high-density design. figure 1 Write circuit diagrams for state-of-the-art memory cells and single-ended bit lines, such as figure 1 shown. The existing circuit includes: a driving circuit 103 and a storage unit 101 . D represents buffered or latched data, BL (bitline) represents a bit line, WL (word line) represents a word line, and I1 and I5 are two inverters. Generally, several memory cells are connected to the bit line BL, but the word line WL signals of these memory cells are respectively connected to different word lines. [0003] When the data D is to be written into a memory cell through the bit line, the data D first drives the bit line BL through the in...

AI Technical Summary

Problems solved by technology

Disadvantages of the existing technology: the bit line is rail-to-rail, so the power consumption required to complete the write operation is relatively large

The disadvantages of various write operations mentioned above: most of them are used in memory cells with differential structures, not suitable for single-ended bit line structures, and most of them use additional voltage sources to achieve low swing

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