Method for reducing power consumption of integrated circuit system of Ethernet passive optical network physical layer

A passive optical network and integrated circuit technology, applied in the selection device of multiplexing system, transmission system, digital transmission system, etc., can solve the problems of delay, difficult operation, poor flexibility, etc., and reduce peak power consumption , reduce peak power consumption, achieve simple effect

Inactive Publication Date: 2012-07-25
SOUTHEAST UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It is difficult to further improve power consumption without the emergence of next-generation manufacturing processes
[0008] 2) For design developers, they can only touch the front-end design and cannot participate in the development of the back-end manufacturing process, so the flexibility is poor
[0009] 3) The adoption of new technology will bring about changes in product costs
[0014] 1) This solution can save the power consumption of the circuit system when it is idle, but it cannot reduce the power consumption when it is running at full load, that is, it cannot reduce the peak power consumption of the system;
[0015] 2) Since the solution of technology 2 can only reduce the power consumption during idle time, it cannot reduce the peak power consumption of the system; and the power system and heat dissipation system of the

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  • Method for reducing power consumption of integrated circuit system of Ethernet passive optical network physical layer
  • Method for reducing power consumption of integrated circuit system of Ethernet passive optical network physical layer
  • Method for reducing power consumption of integrated circuit system of Ethernet passive optical network physical layer

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Experimental program
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specific Embodiment approach 1

[0104] figure 1 Among them, "integrated circuit 101" refers to an integrated circuit that is applied in the physical layer circuit system of an Ethernet device, has certain functional unit properties, and is packaged as a certain circuit element, such as a processor chip, a memory chip, and the like. Its implementation can be a field programmable gate array or a fully customized ASIC.

[0105] figure 1 In , "off-chip electrical connection 102" refers to the circuit connection between integrated circuits and integrated circuits, generally in the form of metal wiring on a printed circuit board.

[0106] figure 1 In , the "input and output interface 103" marked by 1-N refers to a group of I / O ports used to transmit parallel data in the integrated circuit. Generally used to transmit high / low level digital logic signals. The internal functional circuit needs to input (or output) the parallel digital logic signal, which will be input (or output to the electrical connection line ...

specific Embodiment approach 2

[0135] The second embodiment is mainly to adjust and improve the detailed workflow of the codec device and the codec method adopted.

[0136] Because in some cases, if the encoding scheme of the first embodiment is adopted, the effect of reducing I / O unit flipping may decrease with the increase of the parallel I / O bit width. Especially when transmitting some specific data types (such as floating-point data with only a small change in part of the mantissa in the two cycles before and after the transmission). Therefore, the second embodiment proposes an improved method to split the data to be encoded into multiple segments. Depending on the type of binary parallel data to be transmitted, multiple segments can be encoded separately, or only some of the sub-segments can be encoded.

[0137] The flowchart of the encoding method is as follows Figure 5 shown.

[0138] Step 510: first read in the data to be encoded in the current clock cycle;

[0139] Step 520: Split the data int...

Embodiment approach 3

[0152] The difference between Embodiment 3 and Embodiment 1 is that due to the adjustment and improvement of the workflow of the encoding and decoding device and the adopted encoding and decoding methods, the encoding process will not generate flag bits that require additional I / O port transmission, thus Saves the number of I / O ports.

[0153] Since the third embodiment does not add an additional integrated circuit I / O port or an additional off-chip electrical connection, when it is applied to the physical layer circuit system of an Ethernet device, the existing printed circuit board, the direct electrical connection of the integrated circuit, etc. No modifications are required.

[0154] The encoding method flow is as follows Figure 7 shown.

[0155] Now take an 8-bit wide I / O bus as an example:

[0156] Step 700: setting a counter and checking the value of counter N;

[0157] Step 710: judge whether the value of the counter N is 7;

[0158] Step 720: If N is not 7, read...

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Abstract

The invention relates to a method for reducing power consumption of an integrated circuit system of an Ethernet passive optical network physical layer and designs a device for reducing power consumption of I/O (input/output) unit of an integrated circuit. The device is used as a module capable of being integrated into a physical layer integrated circuit. The method includes: encoding data before parallel binary data are transmitted to an I/O interface, computing the number of binary bits changed in two group data in adjacent clock period, turning and setting a zone bit as 1 if the number of changed bits is large; judging whether the data are turned or not according to the zone bits and turning and decoding according to the bits; dividing binary data into multiple sections for parallel I/O with wider bit width, and encoding and decoding the multiple sections; caching n data with bit width of m, grouping the n data and arranging n zone bits into data with bit width of m, and utilizing m-n binary bits without zone bits for checking, wherein the data are used a key frame.

Description

technical field [0001] The invention relates to a method for reducing the power consumption of an Ethernet passive optical network circuit system, mainly through encoding / decoding and a method for optimizing the encoding / decoding mode to reduce the power consumption of the physical layer integrated circuit I / O unit, thereby effectively Minimize the peak power consumption of the system. Background technique [0002] At present, there are three main technical methods to reduce the power consumption of integrated circuit systems: [0003] 1. The technical solution of prior art one [0004] By improving the manufacturing process of the integrated circuit, the power consumption of the physical layer integrated circuit is reduced, thereby reducing the power consumption of the system. [0005] This is usually achieved by reducing the feature size of CMOS deep submicron integrated circuits. Using a smaller feature size means that the transistor can use a shorter gate length, the...

Claims

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Application Information

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IPC IPC(8): H04Q11/00H04L12/24
Inventor 林叶朱恩顾皋蔚张望伟刘露
Owner SOUTHEAST UNIV
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