9 results about "Parallel I/O" patented technology

The invention discloses a parallel IO system-level parameter tuning method and system, and the method comprises the steps: carrying out the unified representation of the related performances of an IO system through standard measurement data which shields the influence of different processors and system architectures, and determining system parameters; performing measurement on a given platform based on the determined system parameters to obtain a measurement result; and according to program IO characteristics, MPIIO parameters influencing parallel IO performance are screened by using the obtained measurement result, and parameter tuning is realized. Screening parameters are theoretically calculated through standard measurement, repeated operation is not needed, and the cost is low; the method is suitable for programs of different platforms and scales, and generalization is high; the IO performance after tuning is remarkably improved, and the parallel IO tuning problem is effectively solved.

The invention provides a real-time online visualization method and device for multi-resolution grid data, and belongs to the technical field of data processing and visualizing.The method comprises the steps that firstly, grid data are merged into sequence columns in the Z direction to form a multi-resolution stacked grid model, the multi-resolution stacked grid model is stored in an HDF5 file according to resolution levels, and parallel I / O is achieved in combination with MinIO distributed object storage; secondly, a Z-Order index and directory server strategy is designed, and the data scheduling and transmission efficiency is improved; a browser end adopts a virtual quadtree structure to organize data, and realizes multi-thread real-time data receiving in combination with WebWorker and WebSocket, so that the blockage of a main thread is avoided; finally, the LOD level is dynamically selected based on the viewpoint distance, and efficient volume rendering is achieved through a GPU texture array and LOD InfoTexture. According to the method, online real-time updating is supported, the loading delay is remarkably reduced, and the visual frame rate is improved.

This invention provides a method and apparatus for real-time online visualization of multi-resolution grid data, belonging to the field of data processing and visualization technology. First, the grid data is merged into hierarchical columns along the Z-axis to form a multi-resolution stacked grid model, which is then stored in HDF5 files according to resolution levels. Parallel I / O is achieved using MinIO distributed object storage. Second, a Z-Order index and directory server strategy are designed to improve data scheduling and transmission efficiency. On the browser side, a virtual quadtree structure is used to organize the data, and WebWorker and WebSocket are used to achieve multi-threaded real-time data reception, avoiding main thread blocking. Finally, the LOD level is dynamically selected based on the viewpoint distance, and efficient volume rendering is achieved using GPU texture arrays and LODInfoTexture. This method supports online real-time updates, significantly reduces loading latency, and improves the visualization frame rate.

This invention relates to the field of semiconductor manufacturing virtual simulation technology, and discloses a method and system for simulating hardware communication protocols. This scheme achieves asynchronous decoupled communication between AMHS services and machine services through message queues (such as MQ), replacing the traditional hardware parallel I / O interaction method. The core includes: defining a protocol format for packaging multi-bit signals (such as 16-bit binary numbers); encoding signals such as VALID and CS_0 into single sequence messages (such as hexadecimal "4030"); maintaining a predefined sequence list (indexing corresponding communication steps) and the latest sequence status; and verifying whether a new message matches the expected sequence. If it matches, the status is updated and the process is advanced; otherwise, it is rejected and reset. The system includes AMHS services, machine services, message queue components, a storage module, and a verification module. This invention solves the problems of service dependency, bandwidth waste, and complex sequence verification in virtual scenarios, significantly improving simulation efficiency and realism, and is suitable for the interactive simulation of AMHS and machine interactions in semiconductor FAB plants.

The invention provides an antenna array beam control system based on an FPGA and a CPLD, and belongs to the technical field of beam forming, the system comprises an FPGA control module and a CPLD logic module, the CPLD logic module is in communication connection with the FPGA control module, the CPLD logic module is connected to a TR assembly module through a multi-path parallel I / O port, the FPGA control module receives control code elements and integrates the control code elements into a command frame, and the command frame is connected to the TR assembly module through a multi-path parallel I / O port. The CPLD logic module receives and analyzes the command frame to obtain control information, and transmits a control code element to the TR component module for beam control according to the control information; the invention further provides an antenna array beam control method based on the FPGA and the CPLD. A serial-to-parallel conversion chip or an additional FPGA chip is not needed, the test layout area and additional FPGA I / O resources are saved, and the cost is greatly reduced.

The application discloses a kind of fine granularity parallel I / O performance prediction and I / O strategy recommendation method and system, the method includes: based on dynamic library intercepting technology collection and I / O performance related fine granularity data and store, obtain performance record set;The data of set is classified, forms n classified sets according to classification rule, constructs and trains performance prediction model for each classified set;By calling performance prediction model, the total performance overhead of each strategy in candidate I / O strategy is calculated, and the I / O strategy with the minimum performance overhead is selected as the optimization recommendation scheme.The application scheme can comprehensively capture the performance characteristics of parallel I / O function, realize high-precision performance prediction using fine-grained I / O performance data, identify the I / O performance bottleneck of large-scale parallel application program by analyzing fine-grained information, realize the performance tuning of application program's I / O module and the performance optimization of overall program, and effectively improve the performance of overall application.

This invention provides a parallel I / O write consistency guarantee method based on state preheating, belonging to the field of computer technology. This invention collects the I / O operation timestamp sequence of MPI processes and the inter-process communication topology, and uses a risk assessment model fused with temporal causal convolution and graph attention to output risk scores for each variable's write operation. It then uses an adaptive preheating timing estimation algorithm based on a queuing network to calculate the expected completion time variance of the I / O path, determining whether to trigger the preheating process. Finally, it uses a preheating intensity adjustment function to fuse the risk scores, MPI process size, and historical write success rate, triggering policy upgrades and retrying when deviations are detected. The execution results are updated with reinforcement learning reward signals to update the parameters of the artificial intelligence model and the weights of the policy decision model, achieving closed-loop adaptive adjustment. This solves the technical problem that parallel I / O write consistency guarantee mechanisms cannot adaptively adjust the synchronization strategy strength according to the real-time system load status and the risk of abnormal propagation between processes.

This invention relates to the field of industrial automation measurement, and discloses a point spectral intelligent controller and its measurement method. The controller includes a communication interface module, a data acquisition and synchronization module, a storage module, and a data processing module. The method includes: S1, constructing an original measurement vector matrix containing distance information and multi-band light intensity information; S2, performing adaptive filtering on the original measurement vector matrix; S3, extracting the surface normal vector and calculating the spatial tilt angle; S4, performing inverse rotation correction of geometric height and bidirectional reflectance distribution function compensation of spectral intensity; S5, calculating the flatness index and outputting the measurement results. This invention uses an FPGA to construct a parallel I / O controller and global synchronization trigger logic in the data acquisition and synchronization module, combined with a direct memory access transmission mechanism, thereby enabling nanosecond-level synchronous exposure of all measurement points and achieving high-speed throughput of large-scale matrix data, effectively eliminating time distortion during dynamic measurement.

The utility model discloses a mode switching control device with a valve position memory function, which comprises an upper computer, an electric valve serving as an actuator, and a single-chip microcomputer serving as a tail end controller and embedded in the electric valve, and is characterized in that the single-chip microcomputer is a single-chip microcomputer; comprising a central processing unit (CPU), a random access memory (RAM), a read-only memory (ROM), a parallel input / output (I / O) interface, a serial communication interface, a timer / counter, an interrupt system, a system clock and a system bus functional component, and the functional components are packaged in an integrated circuit chip with a fixed size. Each I / O interface of the single-chip microcomputer is connected with each sensor and each actuator, and a communication interface is configured with a communication network. Signal transmission and conversion links are reduced, and the oscillation problem in operation and control is reduced; good flexibility and expansibility are realized; batch product single-chip microcomputers and a mature network technology are adopted, so that the system is reliable in control and low in cost.