4 results about "Parallel I/O" patented technology

This invention provides a method and apparatus for real-time online visualization of multi-resolution grid data, belonging to the field of data processing and visualization technology. First, the grid data is merged into hierarchical columns along the Z-axis to form a multi-resolution stacked grid model, which is then stored in HDF5 files according to resolution levels. Parallel I / O is achieved using MinIO distributed object storage. Second, a Z-Order index and directory server strategy are designed to improve data scheduling and transmission efficiency. On the browser side, a virtual quadtree structure is used to organize the data, and WebWorker and WebSocket are used to achieve multi-threaded real-time data reception, avoiding main thread blocking. Finally, the LOD level is dynamically selected based on the viewpoint distance, and efficient volume rendering is achieved using GPU texture arrays and LODInfoTexture. This method supports online real-time updates, significantly reduces loading latency, and improves the visualization frame rate.

This invention provides a parallel I / O write consistency guarantee method based on state preheating, belonging to the field of computer technology. This invention collects the I / O operation timestamp sequence of MPI processes and the inter-process communication topology, and uses a risk assessment model fused with temporal causal convolution and graph attention to output risk scores for each variable's write operation. It then uses an adaptive preheating timing estimation algorithm based on a queuing network to calculate the expected completion time variance of the I / O path, determining whether to trigger the preheating process. Finally, it uses a preheating intensity adjustment function to fuse the risk scores, MPI process size, and historical write success rate, triggering policy upgrades and retrying when deviations are detected. The execution results are updated with reinforcement learning reward signals to update the parameters of the artificial intelligence model and the weights of the policy decision model, achieving closed-loop adaptive adjustment. This solves the technical problem that parallel I / O write consistency guarantee mechanisms cannot adaptively adjust the synchronization strategy strength according to the real-time system load status and the risk of abnormal propagation between processes.

This invention relates to the field of industrial automation measurement, and discloses a point spectral intelligent controller and its measurement method. The controller includes a communication interface module, a data acquisition and synchronization module, a storage module, and a data processing module. The method includes: S1, constructing an original measurement vector matrix containing distance information and multi-band light intensity information; S2, performing adaptive filtering on the original measurement vector matrix; S3, extracting the surface normal vector and calculating the spatial tilt angle; S4, performing inverse rotation correction of geometric height and bidirectional reflectance distribution function compensation of spectral intensity; S5, calculating the flatness index and outputting the measurement results. This invention uses an FPGA to construct a parallel I / O controller and global synchronization trigger logic in the data acquisition and synchronization module, combined with a direct memory access transmission mechanism, thereby enabling nanosecond-level synchronous exposure of all measurement points and achieving high-speed throughput of large-scale matrix data, effectively eliminating time distortion during dynamic measurement.

The utility model discloses a mode switching control device with a valve position memory function, which comprises an upper computer, an electric valve serving as an actuator, and a single-chip microcomputer serving as a tail end controller and embedded in the electric valve, and is characterized in that the single-chip microcomputer is a single-chip microcomputer; comprising a central processing unit (CPU), a random access memory (RAM), a read-only memory (ROM), a parallel input / output (I / O) interface, a serial communication interface, a timer / counter, an interrupt system, a system clock and a system bus functional component, and the functional components are packaged in an integrated circuit chip with a fixed size. Each I / O interface of the single-chip microcomputer is connected with each sensor and each actuator, and a communication interface is configured with a communication network. Signal transmission and conversion links are reduced, and the oscillation problem in operation and control is reduced; good flexibility and expansibility are realized; batch product single-chip microcomputers and a mature network technology are adopted, so that the system is reliable in control and low in cost.