Fault-tolerant deflection routing method and device for bufferless network-on-chip

Abstract

The invention discloses a fault-tolerant deflection routing method and device for a bufferless network-on-chip. The method comprises the following steps of: (1) connecting adjacent routers by configurable bidirectional transmission links; (2) coding before sending a data packet, decoding after receiving the data packet, and entering next step when decoding occurs appointed error; (3) pausing the error chain circuit, detecting the chain circuit, if error does not exist during detection, restoring the chain circuit, otherwise, marking the chain circuit to be faulty; and (4) allocating the transmission direction of the chain circuit with unidirectional fault according to the receiving and sending conditions at two ends of the normal chain circuit. The device comprises routers and a direction dispenser for controlling the transmission direction of the chain circuit between the adjacent routers, wherein each router comprises a computing unit, an exchange dispenser, a cross bar switch, a packet updating unit, multiple registers, a testing control unit and multiple direction-allocable transmission control units which are corresponding to the registers. The method and device have the advantages of good fault tolerance, high chain circuit utilization rate and small area expense.

Description

technical field [0001] The invention relates to an on-chip router structure in the field of multi-core microprocessors, in particular to a fault-tolerant deflection routing method and device applied to a non-buffer on-chip network. Background technique [0002] In recent years, with the reduction of integrated circuit process size and the improvement of integration level, more and more processor cores can be integrated on a single chip. Network-on-Chip (NoC) technology has gradually become a standard communication architecture for on-chip interconnection of single-chip multiprocessors (Chip-Multiprocessors, CMPs). However, as integrated circuit technology enters the nanometer era, smaller feature sizes, lower power supply voltages, and increasing clock frequencies seriously affect the reliability of very large-scale integrated circuits (VLSI circuits). [0003] Network-on-chip is mainly affected by two types of faults: transient faults and permanent faults. Transient fault...

AI Technical Summary

Problems solved by technology

In most existing fault-tolerant routing algorithms, there are usually three types of problems: one is to simplify the fault model to avoid deadlock or livelock, and cannot handle arbitrary fault modes; the other is to configure the routing table offline To deal with more complex fault models; third, it cannot guarantee the "zero loss rate" of packets, but can only improve the packet arrival rate under fault conditions

However, in actual situations, the probability of two-way link failures at the same time is low, and equating unidirectional link failures to bidirectional failures will reduce the efficiency of the network

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