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Forming method of metal grid electrode

A metal gate and pseudo gate technology, which is applied in the fields of electrical components, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve the problems of reducing the electrical performance of semiconductor devices, short-circuiting semiconductor devices, and increasing the effective thickness of the gate insulating film. The effect of reducing the possibility of metal bridging and metal residue, improving electrical performance and reliability

Active Publication Date: 2012-08-15
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] Previously, polysilicon gates and polysilicate gates, etc. were used as gates in semiconductor devices, and polysilicon gates had problems in that the effective thickness of the gate insulating film increased due to the The phenomenon of P+ or N+ polysilicon gate penetration into the substrate and the change of threshold voltage caused by the change of dopant distribution, etc.
continue as Figure 7 As shown, since there are relatively large depressions on the surface of the interlayer dielectric layer 6, after forming the metal gate 10, there will be a metal layer remaining on the surface of the interlayer dielectric layer 6, which will cause a short circuit in the semiconductor device formed subsequently, reducing the electrical properties of semiconductor devices

Method used

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  • Forming method of metal grid electrode
  • Forming method of metal grid electrode
  • Forming method of metal grid electrode

Examples

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no. 1 example

[0045] Such as Figure 8 As shown, the first embodiment of forming a metal gate provided by the present invention includes:

[0046] S110, providing a semiconductor substrate, forming a dummy gate structure on the semiconductor substrate, the dummy gate structure including: a gate dielectric layer on the semiconductor substrate and a dummy gate electrode layer on the gate dielectric layer, the There are sidewalls on the semiconductor substrate on both sides of the dummy gate electrode layer; a barrier layer is formed on the semiconductor substrate, and the barrier layer surrounds the sidewall and the dummy gate electrode layer; on the semiconductor substrate forming an interlayer dielectric layer on the dummy gate structure;

[0047] S120, grinding the interlayer dielectric layer to expose the surface of the barrier layer above the dummy gate electrode layer;

[0048] S130, grinding the interlayer dielectric layer and the barrier layer to expose the dummy gate electrode laye...

no. 2 example

[0082] like Figure 16 As shown, the second embodiment of forming a metal gate provided by the present invention includes:

[0083] S210, providing a semiconductor substrate, forming a dummy gate structure on the semiconductor substrate, the dummy gate structure including: a gate dielectric layer on the semiconductor substrate and a dummy gate electrode layer on the gate dielectric layer, the There are sidewalls on the semiconductor substrate on both sides of the dummy gate electrode layer; a barrier layer is formed on the semiconductor substrate, and the barrier layer surrounds the sidewall and the dummy gate electrode layer; on the semiconductor substrate forming an interlayer dielectric layer on the dummy gate structure;

[0084] S220, grinding the interlayer dielectric layer to expose the surface of the barrier layer above the dummy gate electrode layer;

[0085] S230, grinding the interlayer dielectric layer and the barrier layer to expose the dummy gate electrode layer...

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Abstract

The invention relates to a forming method of a metal grid electrode in the field of the semiconductor manufacture. The method comprises the following steps that: a semiconductor substrate is provided, and a forged grid structure is formed on the semiconductor substrate; an interlayer dielectric layer is formed on the forged grid structure and the semiconductor substrate; the interlayer dielectric layer is ground until the upper surface of the forged grid structure is exposed out, and a nature oxidation layer is formed on the upper surface of the forged grid structure; and the nature oxidation layer is removed through a chemical gas phase etching process. The forming method has the advantages that during the nature oxidation layer removal, the influence on the interlayer dielectric layer recess is reduced, the possibility of generating metal bridge connection and metal residue in the interlayer dielectric layer is greatly reduced, and the electric performance and the reliability of the semiconductor device are improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a metal gate. Background technique [0002] Previously, polysilicon gates and polysilicate gates, etc. were used as gates in semiconductor devices, and polysilicon gates had problems in that the effective thickness of the gate insulating film increased due to the The phenomenon of P+ or N+ polysilicon gate penetration into the substrate and the change of threshold voltage caused by the change of dopant distribution, etc. There is also a problem that a conventional polysilicon gate cannot achieve a low resistance value on a line with a narrow width. [0003] In order to solve the above problems, the prior art not only solves the problems caused by the existing polysilicon gates by not using dopants in the manufacture of metal gates, but also, as metal gates, by making the work function in the middle of silicon A metal with a bandgap that can symmet...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/28H01L21/311
Inventor 陈枫刘焕新
Owner SEMICON MFG INT (SHANGHAI) CORP