Enhanced global alignment (EGA) mark and photolithograph pattern

Abstract

The invention discloses an enhanced global alignment (EGA) mark and a photolithograph pattern. The photolithograph pattern comprises a first-direction scribe line and a second-direction scribe line intersecting with the first-direction scribe line, wherein the first direction is perpendicular to the second direction; and an EGA mark arranged at a cross point of the first-direction scribe line and the second-direction scribe line. The EGA mark comprises a plurality of first strip marks which are spaced from one another at a uniform pitch and parallel to one another along the first direction in the first-direction scribe line, and constitute a first strip mark array; and a plurality of second strip marks which are spaced from one another at a uniform pitch and parallel to one another along the second direction in the second-direction scribe line, and are symmetrically arranged at two sides of the first strip mark array. A length of the first strip marks in the distribution region in the first direction is larger than that of the second strip mark. The alignment and overlay accuracy is improved in the case that the width of the scribe line is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an enhanced global alignment mark and a photolithography layout. Background technique [0002] With the continuous improvement of integrated circuit manufacturing technology and the continuous reduction of line width, the layout of semiconductors has evolved from ordinary single-function discrete devices to integrated high-density and multi-functional integrated circuits. [0003] In the current semiconductor manufacturing process, before semiconductor devices are fabricated on the wafer, the wafer needs to be layout designed, and the wafer is divided into several unit areas (Die) and scribe lanes (Scribe lanes) between the unit areas. The unit area is used to subsequently form a semiconductor device, and the dicing line is used as a cutting line for dividing the unit area (Die) in the packaging stage when the semiconductor device is manufactured. [0004] Photolithogr...

AI Technical Summary

Problems solved by technology

[0008] The width of the existing cutting lines is generally greater than or equal to 80 microns, but with the continuous development of cutting technology, the width of the cutting lines is becoming narrower, such as: 60 microns, 50 microns, the enhanced global alignment mark formed in the cutting line The width and length should also be correspondingly reduced. During photolithographic alignment, it will make it difficult to identify the signal, affect the accuracy of alignment, and cause the offset of overlay

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