Manufacturing method of transistor

Abstract

The invention discloses a manufacturing method of a transistor, which comprises that: a substrate is provided, the transistor is formed on the substrate, and the transistor comprises a grid electrode positioned on the substrate; a stop layer is covered on the transistor; a medium layer structure is covered on the stop layer; a first leveling process is carried out on the medium layer structure until the stop layer on the grid electrode is exposed; the stop layer on the grid electrode and the remaining medium layer structure are removed until the grid electrode is exposed to enable upper surfaces of the stop layer and the medium layer structure are below the upper surface of the grid electrode; a insulation material is deposited on the grid electrode, the stop layer and the medium layer structure to form an interlaminating medium layer; and a second leveling process is carried out on the interlaminating medium layer until the grid electrode is exposed. According to the manufacturing method, a bucktooth effect of the transistor can be avoided.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a transistor. Background technique [0002] With the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions of semiconductor devices, semiconductor chips are developing towards higher integration. The higher the integration degree of the semiconductor chip, the smaller the critical dimension (CD, Critical Dimension) of the semiconductor device. At present, in VLSI, the feature size has entered the range of tens to hundreds of nanometers. [0003] For semiconductor devices with a feature size smaller than 32nm, transistors using high-K metal gates are the mainstream technology, refer to figure 1 ~Reference Figure 4 A schematic diagram of an embodiment of a prior art transistor manufacturing method is shown. [0004] First, please refer to fig...

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Problems solved by technology

[0007] continue to refer Figure 4 , the silicon nitride on the gate 14 is removed by a third CMP process. In the third CMP process, abrasives (slurry) tend to gather at the interface between the first silicon oxide layer 12 and the barrier layer 11 of silicon nitride material , so that a depression 17 is formed at the junction of the first silicon oxide layer 12 and the barrier layer 11. The depression 17 will affect the subsequent manufacturing process, for example: the subsequent CMP process will be performed on Al, and in the CMP process, the aluminum material will remain in the depression. 17, it will also cause the problem of gate height reduction, etc.

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