Built-in self test and built-in self-repairing technology of TSV (Through Silicon Via) interconnection of 3D chip

Abstract

The invention relates to a built-in self test and built-in self-repairing technology of TSV (Through Silicon Via) interconnection of a 3D chip. The technology comprises the following steps: at the chip-designing stage, corresponding built-in self test and built-in self-repairing circuits are inserted, and a redundant TSV channel is designed; after power-on reset of the 3D chip, the built-in self test circuit starts to work, carries out grouped test on TSVs, generates corresponding TSV configuration information according to a test result, and then calls the built-in self-repairing circuit for configuration of a TSV mapping circuit, and simultaneously, the test of next group of TSVs is started; after the test and the configuration on all the TSVs, the circuits can enter normal working. The technology has the advantages that the difficulty of the TSV interconnection in the traditional 3D chip can be solved, the strategy can be replaced by redundancy, and the finished-product rate of the 3D chip is increased; the dependency of the 3D chip test on ATE (Automatic Test Equipment) is reduced, so that the test cost of the 3D chip is reduced; and due to independency from the specific chip function, the technology can be widely applied to the 3D chip based on the TSVs and has stronger practicability.

Description

technical field [0001] The invention discloses a built-in self-test and built-in self-repair technology for 3D chip TSV (through-silicon via) interconnection. Specifically, after the 3D chip is powered on and reset (Power-on Reset), the built-in self-test circuit starts to work, conducts group tests on TSVs, generates corresponding TSV configuration information according to the test results, and then calls the built-in self-repair circuit to TSV is configured, and when all TSV tests and configurations are completed, the circuit can enter normal operation. Background technique [0002] With the reduction of device size and the increase of circuit scale, the problems of delay and power consumption caused by interconnect lines are becoming more and more serious. In fact, this has become the most important bottleneck restricting circuit performance. The 3D chip realizes the vertical interconnection of multi-layer silicon wafers through silicon via technology, which increases th...

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Problems solved by technology

Hung-Yen Huang et al. proposed a built-in self-test and built-in self-repair scheme for TSV interconnection. It is a simulation test technology by equating TSV to an RC model for charge and discharge testing, but the RC model of TSV The accuracy of the

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