Array substrate, manufacturing method and display device thereof

Abstract

The invention provides an array substrate, a manufacturing method and a display device thereof, and relates to the technical field of display. The invention aims to reduce the production difficulty of the array substrate, simplify the manufacturing process of the array substrate and reduce the production cost. The array substrate comprises a thin-film transistor, wherein the thin-film transistor is formed by contact of a top grid positioned on a substrate; a grid electrode and a grid line of the thin-film transistor are connected, a source electrode is connected with a data line, and a drain electrode is connected with a pixel electrode. The manufacturing method of the array substrate comprises the following steps of: forming a graph including the source-drain electrodes, the pixel electrode and the data line on the substrate by a first-time composition process; forming a graph including a semiconductor layer, a grid-electrode insulating layer, the grid electrode and the grid line by a second-time composition process; and forming a graph including a passivation layer and passivation layer through holes by a third-time composition process. The display device comprises the array substrate.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device. Background technique [0002] Transistors are used as switching and driving devices to control and drive flat panel displays, such as liquid crystal displays, electroluminescent displays, and the like. Currently, thin film transistors of bottom-gate bottom-contact configuration and bottom-gate top-contact configuration are widely used in array substrates of liquid crystal displays. [0003] Such as figure 1 As shown, the gate 1 of the thin film transistor with the bottom-gate-bottom-contact configuration is prepared on the substrate 3, the gate 1 is above the gate insulating layer 4, and the source and drain electrodes 2 are between the gate insulating layer 4 and the semiconductor film 5 , the boundary of the source-drain electrodes 2 under this structure will affect the deposition of the semico...

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Problems solved by technology

[0003] like figure 1 As shown, the gate 1 of the thin film transistor with the bottom-gate-bottom-contact configuration is prepared on the substrate 3, the gate 1 is above the gate insulating layer 4, and the source and drain electrodes 2 are between the gate insulating layer 4 and the semiconductor film 5 , the boundary of the source-drain electrodes 2 under this structure will affect the deposition of the semiconductor thin film 5, which will reduce the molecular arrangement of the semiconductor thin film 5, thereby affecting the transport of its carriers, reducing the performance of the device, and further affecting the array substrate. quality; such as figure 2 As shown, the gate 1 of the thin film transistor with the bottom-gate top-contact configuration is also prepared on the substrate 3, the gate 1 is above the gate insulating layer 4, and the semiconductor film 5 is prepared on the gate insulating layer 4. Metal electrodes are regrown on the semiconductor film 5 to form the source-drain electrodes 2. The manufacturing process of the source-drain electrodes 2 under this structure is greatly limited, and the preparation of the source-drain electrodes 2 will cause damage to the organic semiconductor films that have been arranged in an orderly manner. , generally can only be formed by thermal evaporation, which is difficult to produce

At the same time, the existing array substrates of thin-film transistors with a bottom-gate bottom-contact configuration and a bottom-gate top-contact configuration require multiple photolithographic masks during the preparation process, which is cumbersome and expensive to produce.

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