multiplier
A technology of multipliers and multipliers, which is applied in the fields of instruments, electrical digital data processing, digital data processing components, etc., can solve the problems of multiplier structure complexity and measurement accuracy, and achieve the effect of reducing the area
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no. 1 example
[0035] figure 2 A circuit configuration diagram of the multiplier of the present invention in the first embodiment is shown. Such as figure 2 As shown, the multiplier in the first embodiment includes: a bit selection unit 11 , a Booth encoding unit 12 , a partial accumulated value gate unit 13 , an addition unit 14 , a register unit 15 , and a clock control unit 16 .
[0036] Each of the above unit components will be described in detail below.
[0037] The clock control unit 16 is used to generate a clock control signal. In this embodiment, the clock control unit 16 generates: the first clock control signal Ctrl1 for controlling the bit selection unit 11, the second clock control signal Ctrl2 for controlling the partially accumulated value gating unit 13, and the control register unit 15. The third clock control signal Ctrl3.
[0038] The bit selection unit 11 is used for selecting bits of the multiplier based on Radix-4Booth coding. Here, the multiplier has N bits.
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no. 2 example
[0056] Figure 4 A circuit configuration diagram of the second embodiment of the multiplier of the present invention is shown. Such as Figure 4 As shown, the multiplier in the second embodiment includes: a multiplier gating unit 21, a bit selection unit 22, a multiplicand control unit 23, a multiplicand gating unit 24, a Booth encoding unit 25, and a part of accumulated value A gating unit 26 , an adding unit 27 , a first register unit 28 , a second register unit 29 and a clock control unit 20 .
[0057] Each of the above unit components will be described in detail below.
[0058] The clock control unit 20 is used to generate the first clock control signal Ctrl1 of the control bit selection unit 22 and the multiplicand control unit 23, the second clock control signal Ctrl2 of the control part accumulation value gating unit 26, and control the second register The third clock control signal Ctrl3 of unit 29;
[0059] The multiplier gating unit 21 is used to select one of th...
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