Dynamic group association cache device for processor and access method thereof

Abstract

The invention provides a dynamic group association cache device for a processor. The device firstly judges the effective bit of each cache block in a cache group to be accessed during a reading access, sets the enabled bit of the cache route at which the cache block is located according to the effective bit of each cache block, reads the effective cache block and compares the marked segment in the access address with the marked block of each cache block; and if hitting the target, the device reads the data from the data block of the cache block hitting the target according to the offset segment in the access address. In the procedure executing process, the device dynamically changes the degree of association of the cache device and filters the reading operation of ineffective cache blocks, thereby effectively reducing the power consumption of cache under the condition that the design complexity is basically not increased and the performance of the processor is not affected, so that the power consumption of the whole processor is lowered.

Description

technical field [0001] The present invention relates to processor design, and more particularly to processor cache design. Background technique [0002] For a long time, in order to alleviate the "storage wall" problem between the processor and the memory, that is, the processing speed of the processor is much faster than the supply speed of the memory, causing the processor to be in a "starved" and waiting state, the cache is used in in the structure of the processor. The processor's cache uses the principles of locality of program access, including temporal locality—the memory address being accessed is accessed again in a relatively short period of time, and spatial locality—a memory address is accessed near it. The storage address of the memory will also be accessed in a short period of time, making up the speed gap between the processor and the memory, thereby greatly improving the performance of the processor. In general, for most programs, larger cache devices tend t...

AI Technical Summary

Problems solved by technology

However, existing methods for reducing cache power consumption either require software support, or at the cost of performance loss, or introduce excessive hardware overhead, increasing implementation complexity

Images