Dynamic group association cache device for processor and access method thereof

A high-speed cache and processor technology, applied in memory architecture access/allocation, electrical digital data processing, digital data processing components, etc., can solve problems such as increased implementation complexity and performance loss, and achieve increased design complexity and reduced Power consumption, the effect of reducing dynamic power consumption

Active Publication Date: 2012-09-12
INST OF COMPUTING TECH CHINESE ACAD OF SCI +1
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

However, existing methods for reducing cache power consumption either require software support, or at the

Method used

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  • Dynamic group association cache device for processor and access method thereof
  • Dynamic group association cache device for processor and access method thereof
  • Dynamic group association cache device for processor and access method thereof

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Embodiment Construction

[0031] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0032] The power consumption of the cache is divided into dynamic power consumption and static power consumption. Dynamic power consumption refers to the power consumption of capacitor charging and discharging and short-circuit power consumption, which is mainly caused by the flipping of the circuit when reading and writing the cache. Static power consumption refers to leakage current power consumption, which is the power consumption when the circuit state is stable.

[0033] According to the analysis and statistics of the SPEC (The Standard Performance Evaluation Corporation) CPU2000...

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Abstract

The invention provides a dynamic group association cache device for a processor. The device firstly judges the effective bit of each cache block in a cache group to be accessed during a reading access, sets the enabled bit of the cache route at which the cache block is located according to the effective bit of each cache block, reads the effective cache block and compares the marked segment in the access address with the marked block of each cache block; and if hitting the target, the device reads the data from the data block of the cache block hitting the target according to the offset segment in the access address. In the procedure executing process, the device dynamically changes the degree of association of the cache device and filters the reading operation of ineffective cache blocks, thereby effectively reducing the power consumption of cache under the condition that the design complexity is basically not increased and the performance of the processor is not affected, so that the power consumption of the whole processor is lowered.

Description

technical field [0001] The present invention relates to processor design, and more particularly to processor cache design. Background technique [0002] For a long time, in order to alleviate the "storage wall" problem between the processor and the memory, that is, the processing speed of the processor is much faster than the supply speed of the memory, causing the processor to be in a "starved" and waiting state, the cache is used in in the structure of the processor. The processor's cache uses the principles of locality of program access, including temporal locality—the memory address being accessed is accessed again in a relatively short period of time, and spatial locality—a memory address is accessed near it. The storage address of the memory will also be accessed in a short period of time, making up the speed gap between the processor and the memory, thereby greatly improving the performance of the processor. In general, for most programs, larger cache devices tend t...

Claims

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Application Information

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IPC IPC(8): G06F12/08G06F12/0831G06F12/0864G06F12/0891G06F12/0895
CPCG06F12/0895G06F1/3275G06F12/0891G06F2212/601Y02D10/00Y02B70/10G06F2212/6032G06F12/0833G06F12/0864G06F2212/621
Inventor 范灵俊唐士斌王达张浩范东睿
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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