Insertion method for filling redundant polysilicon strip arrays in existing layout

Abstract

The utility model discloses an insertion method for filling redundant polysilicon strip arrays in the existing layout. The insertion method comprises the following steps of: extracting the position information of standard cells; sequencing the position of the standard cells; judging whether distance exists between the adjacent standard cells or not; if the distance exists, respectively inserting the redundant polysilicon strip arrays into the opposite borders of the two adjacent standard cells; if the distance does not exist, inserting the redundant polysilicon strip arrays into the borders of the two adjacent standard cells in a shared mode; and moreover, checking layout design rules and the consistence of the layout and a schematic diagram to the layout where the redundant polysilicon strip arrays are inserted. Based on the current ASIC (Application Specific Integrated Circuit) design flow, the method optimizes the designed layout, and a standard cell library needs not to be modified, so that the operation is simple and is compatible with the current ASIC design flow. The method only finely adjusts the existing layout, the LVS (Low Velocity Scanning) and DRC (Data Record Control) check of the layout is not influenced, and the area of the layout cannot be increased.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an insertion method for filling redundant polysilicon strip arrays in existing layouts under nanotechnology. Background technique [0002] The parameter yield refers to the percentage of the number of chips that meet the timing and power consumption performance requirements to the number of chips with normal functions. Process fluctuations will cause changes in physical parameters, the most important of which is the change in line width, especially the polysilicon gate line width, that is, the channel length of the MOS transistor. The channel length of the MOS tube is not only the main parameter affecting the performance of the MOS tube, but also the most likely to cause changes due to the smallest line width. Therefore, the line width change caused by process fluctuations mainly refers to the change in the channel length of the MOS tube. The change of the channel le...

AI Technical Summary

Problems solved by technology

[0009] The present invention provides an insertion method for filling redundant polysilicon strip arrays in the existing layout, which solves the problem of inserting redundant polysilicon strips between standard cells only by modifying the standard cell library of the layout in the prior art. Compatible with existing ASIC design flows

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