Forming method of dual-stress silicon nitride etched block layer and manufacturing method of semiconductor device
A technology of silicon nitride etching and barrier layer, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of increasing product cost and increasing the difficulty of process control
Active Publication Date: 2012-10-03
SHANGHAI HUALI MICROELECTRONICS CORP
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However, the above processing method increases the difficulty of process control, and needs to add an extra layout, which increases the cost of the product
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[0024] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.
[0025] The inventors of the present application have advantageously found that tensile stress silicon nitride (such as high tensile stress silicon nitride) will shrink after being irradiated by ultraviolet light, and the shrinkage rate of the film depends on the temperature of film deposition and the conditions of ultraviolet light irradiation. Between 2% and 20%. In the embodiment of the present invention, since the silicon nitride with high tensile stress will shrink after being irradiated with ultraviolet light, after removing the silicon nitride with high tensile stress on the PMOS transistor PM2 and then irradiating with ultraviolet light, the film will shrink, Therefore, the effect of redesigning the layout in the existing method is achiev...
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Abstract
The invention provides a forming method of a dual-stress silicon nitride etched block layer and a manufacturing method of a semiconductor device. The forming method of the dual-stress silicon nitride etched block layer comprises the steps of: providing a semiconductor device with an NMOS (N-channel metal oxide semiconductor) transistor and a PMOS (P-channel metal oxide semiconductor) transistor, and forming a tensile stress layer on the semiconductor device; then shielding the tensile stress layer on the NMOS transistor via a first photoresist layer to enable the tensile stress layer on the PMOS transistor to be exposed; removing the tensile stress layer on the PMOS transistor; removing the first photoresist layer; irradiating a tensile stress silicon nitride layer with ultraviolet light after removal of the first photoresist layer; forming a compressive stress layer on the semiconductor device; shielding the compressive stress layer on the PMOS transistor via a second photoresist layer to enable the compressive stress layer on NMOS transistor to be exposed; removing the compressive stress layer on NMOS transistor; and removing the second photoresist layer.
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing, and more specifically, the invention relates to a method for forming a double-stressed silicon nitride etching barrier layer and a semiconductor device manufacturing method using the method for forming a double-stressed silicon nitride etching barrier layer. Background technique [0002] As the characteristic line width of integrated circuits shrinks below 90nm, people gradually introduce high-stress silicon nitride technology to improve the electrical mobility of carriers. By depositing high-tension and high-voltage stress silicon nitride on NMOS and / or PMOS as a via etch stop layer (Contact Etch Stop Layer, CESL). Especially in the process below 65nm, in order to improve the electrical mobility of NMOS and PMOS at the same time, it is sometimes necessary to simultaneously deposit high-tension and high-voltage stress silicon nitride on different MOSs. [0003] However, as far as curre...
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Login to View More IPC IPC(8): H01L21/318H01L21/8238
Inventor 徐强
Owner SHANGHAI HUALI MICROELECTRONICS CORP