Masking template, static random access storage unit and storage

Abstract

Provided is a masking template with a static random access storage unit graph, a static random access storage unit and a storage. The masking template comprises at least one access N-channel metal oxide semiconductor (NMOS) transistor graph and at least one loading p-channel metal oxide semiconductor (PMOS) transistor graph, the access NMOS transistor graph and the loading PMOS transistor graph are equal in quantity and provided with same first critical dimension, and the access NMOS transistor graph and the loading PMOS transistor graph are arranged in pair and are connected face to face in the direction of the first critical dimension. The static random access storage unit comprises at least one access NMOS transistor and least one loading PMOS transistor, the access NMOS transistor and the loading PMOS transistor are equal in quantity and provided with same first critical dimension, the access NMOS transistor and the loading PMOS transistor are located on a substrate and arranged in pair, and the access NMOS transistor and the loading PMOS transistor are connected face to face in the direction of the first critical dimension. The storage comprises the storage unit. The masking template, the static random access storage unit and the storage are simple and convenient and have no influences on device performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a reticle with a pattern of a static random access memory unit, a static random access memory unit and a memory. Background technique [0002] According to the different ways of storing data, semiconductor memory can be divided into two categories: random access memory (RAM) and read-only memory (ROM). Random access memory (RAM) can be divided into static random access memory (SRAM) and dynamic random access memory (DRAM). Compared with DRAM, SRAM has faster read and write speeds. Moreover, SRAM does not need to periodically refresh the stored information, and its design and manufacture are relatively simple. [0003] The overall structure of SRAM can be divided into two parts: memory bank array and peripheral circuit. Wherein, the memory bank array is composed of a precharge circuit and a memory cell array. In SRAM, the storage unit is its most basic and ...

AI Technical Summary

Problems solved by technology

However, when the driving NMOS transistor is actually made larger than the access NMOS transistor, a certain degree of chamfering will inevitably occur in the parts that need to be made at right angles.

Using such a mask for subsequent steps will eventually affect the performance of the device

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