Semiconductor storage device

Abstract

When plural diffusion layers are shared in order to save an area of a semiconductor integrated circuit, parasitic capacities of wirings coupled to those diffusion layers are changed. Nonetheless, a semiconductor layout balancing capacitive loads of paired wirings coupled to the diffusion layers with each other is provided. The diffusion layers coupled to the respective paired wirings are alternately arranged or staggered to balance the respective capacitive loads of the paired wirings with each other.

Description

[0001] Cross References to Related Applications [0002] The disclosure of Japanese Patent Application No. 2011-087971 filed on Apr. 12, 2011 including specification, drawings and abstract is hereby incorporated by reference in its entirety. technical field [0003] The present invention relates to a semiconductor memory device, and more particularly to a dynamic semiconductor memory device. Background technique [0004] In dynamic semiconductor memory devices, reduction in circuit area is an important task. As a method of reducing the circuit area, there is known a technique of sharing a coupling destination diffusion layer having a switch for column selection of a signal output from a sense amplifier of a folded bit line system by repeating an array structure. [0005] figure 1 is a layout diagram showing a semiconductor layout of an open-bit sense amplifier in a general semiconductor memory device. will describe figure 1 Semiconductor layout of the sense amplifier in ...

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Problems solved by technology

On the other hand, there arises a problem that the difference in capacity between the bus BUS1 and the dummy bus DBUS1 increases with the total area of ​​the diffusion layer coupled with the corresponding line

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