Layout scheme and method for forming device cells in semiconductor devices

Abstract

A method and layout for forming word line decoder devices and other devices having word line decoder cells, providing metal interconnect layers using non-DPL photolithographic operations, and providing using lower or middle metal layers Or the adjacent lead material is stitched to the transistor disposed at the end. Transistors can be placed in or near vertically configured word line decoders or other cells, and wires connected using metal or wire material reduce gate resistance between transistors and avoid RC signal delays. The invention also discloses a layout scheme and method for forming device units in the semiconductor device.

Description

technical field [0001] The present invention relates to a highly integrated layout scheme for device cells located in word line decoder devices or other semiconductor devices using single pattern photolithography. Background technique [0002] Various semiconductor devices employing SRAM cells or other repeating device cells arranged in arrays and connected to each other are used in various applications and perform multiple functions. As an example, word line decoder devices serve a variety of functions in the electronics world and utilize a large number of word line decoder cells and SRAM (Static Random Access Memory) cells. These semiconductor devices typically include layouts that utilize repeating arrays for design convenience. One general layout includes a repeating array of word line decoder cells. This arrangement of repeating cells is advantageous because it represents an established and versatile design that provides a high degree of integration and includes multi...

AI Technical Summary

Problems solved by technology

[0005] While the use of DPL enables tighter pitches to be made in the lower metal pattern that extends the upper metal pattern through void regions in the lower metal pattern for the polysilicon gate stitch routing, the dual Pattern lithography operations come with their inherent drawbacks

One disadvantage associated with using double patterning lithography is the high cost because two photomasks must be fabricated and used

Furthermore, combining two photomasks to form a pattern is fabricated by a mask decomposition method, which can be unreliable and time consuming

In addition to the costs associated with performing each of coating, exposing, and developing photolithography operations twice, and the etching and removal operations twice, the time associated with having to perform each of these operations twice brings Delays in cost and cycle time

Finally, using yet another photomask brings additional inherent risk of misalignment and / or rework

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