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sram write assist device

A write assist and write operation technology, applied in the semiconductor field, can solve the problems of write and read margin reduction, unreliable write and read operations, etc.

Active Publication Date: 2015-11-25
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the lower operating voltage of SRAM cells may reduce write and read margins to low levels
This low level may result in less reliable write and read operations

Method used

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Embodiment Construction

[0034] The making and using of preferred embodiments of the invention are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the disclosure.

[0035] The present invention has been described with reference to a preferred embodiment in a specific context, namely, in a static random access memory (SRAM) write assist device. However, the present invention can also be applied to various memory circuits.

[0036] First, refer to Figure 1A , shows a schematic diagram of an SRAM cell according to an embodiment. SRAM cell 100 includes: a first inverter formed from pull-up PMOS transistor 106 and pull-down NMOS transistor 102 ; and a second inverter formed from pull-up PMOS transistor 108 and pull-down NMOS ...

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PUM

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Abstract

An SRAM write assist apparatus comprises a timer unit and a voltage divider. The voltage divider unit is configured to divide a voltage potential down to a lower level. The output of the voltage divider is connected to a memory cell in a write operation. The timer unit is configured to generate a pulse having a width inversely proportional to the voltage potential applied to a memory chip. Furthermore, the timer unit controls the period in which a lower voltage from the output of the voltage divider is applied to the memory cell. Moreover, external level and timing programmable signals can be used to further adjust the voltage divider's ratio and the pulse width from the timer unit. By employing the SRAM write assist apparatus, a memory chip can perform a reliable and fast write operation.

Description

technical field [0001] The present invention relates to the field of semiconductors, and more specifically, the present invention relates to an SRAM write assist device. Background technique [0002] Modern electronic devices such as laptop computers include various memories for storing information. Memory circuits include two main types. One is volatile memory; the other is non-volatile memory. Volatile memory includes random access memory (RAM), which can be further divided into two subcategories: static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they lose information when power is removed. Non-volatile memory, on the other hand, retains the data stored on it. Non-volatile memory includes various subcategories such as electrically erasable programmable read-only memory (EEPROM) and flash memory. [0003] SRAM cells can include different numbers of transistors. Depending on the total number of transisto...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/4076G11C11/4074
CPCG11C11/419G11C11/41G11C29/021G11C29/023G11C29/028
Inventor 郑基廷邹宗成张琮永
Owner TAIWAN SEMICON MFG CO LTD