Silicon nitride passivation layer for covering high aspect ratio features

Abstract

A method of forming a passivation layer comprising silicon nitride on features of a substrate is described. In a first stage of the deposition method, a dielectric deposition gas, comprising a silicon-containing gas and a nitrogen-containing gas, is introduced into the process zone and energized to deposit a silicon nitride layer. In a second stage, a treatment gas, having a different composition than that of the dielectric deposition gas, is introduced into the process zone and energized to treat the silicon nitride layer. The first and second stages can be performed a plurality of times.

Description

technical field [0001] Embodiments of the invention pertain to forming a passivation layer comprising silicon nitride on high aspect ratio features for use in fabricating electronic circuits on a substrate. Background technique [0002] Electronic circuits, such as integrated, display, memory, power and optoelectronic circuits, are becoming denser and more complex. The dimensions of the features of these circuits are becoming smaller to allow greater air density across the substrate. These features include connector bumps, interconnects, semiconductor or oxide features, gates, electrodes, resistors, vias, and many others. As the width or horizontal dimension of a feature becomes smaller, the aspect ratio of the feature increases because the vertical dimension of the feature must be larger to provide the same cross-sectional area. Aspect ratio (the ratio of the height to width of a feature) is a particular issue when covering the feature with a passivation layer to protect ...

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Problems solved by technology

[0004] However, as the aspect ratio of the interconnect 13 or connector bump 14 increases to values ​​above 0.2, it becomes increasingly difficult to deposit continuous, conformal and substantially defect-free passivation layer 10,

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