Split gate memory and manufacturing method thereof

Abstract

The invention relates to a split gate storage. A tunneling dielectric layer is made of low-k dielectric materials. Since the tunneling dielectric layer of the split gate storage is made of the low-k dielectric materials which are low in dielectric constant, coupling capacitance between a gate dielectric layer and a charge storage layer can be effectively reduced while the thickness of the tunneling dielectric layer of the split gate storage is not increased, erasure operating voltage of the split gate storage can be effectively lowered, and erasure operating speed is effectively increased.

Description

Technical field [0001] The present invention relates to a semiconductor device and manufacturing technology, and more specifically, to a split gate memory and a manufacturing method thereof. Background technique [0002] With the popularity of portable personal devices, non-volatile memory has gradually become a research and development focus in the semiconductor industry due to its advantages such as maintaining a memory state and operating low power consumption when there is no power supply. [0003] Based on the structure of the memory cell, non-volatile memories are generally divided into two categories: stacked gate structure and split gate structure devices (split gate devices). Due to the low-voltage and high-speed operation characteristics, split-gate devices are widely used in embedded storage applications and become the mainstream technology of embedded storage devices. [0004] Such as figure 1 As shown, the conventional split gate memory mainly includes: a source region ...

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Problems solved by technology

[0007] However, the problem with the above-mentioned split gate memory is that silicon dioxide is usually used as the tunneling dielectric layer, so that the coupling capacitance C1 between the control gate dielectric layer and the charge storage layer is relatively large, refer to figure 1 or figure 2 , the required erasing voltage is also large, and the erasing speed is also slow, which affects the performance of the device. To reduce the coupling capacitance C1 between the control gate dielectric layer and the charge storage layer, it is necessary to increase the thickness of the tunneling dielectric layer. Conducive to the reduction of device size and the improvement of chip integration

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