DFT (Design for Testability) method for double-edge trigger

Abstract

The invention discloses a DFT (Design for Testability) method for a double-edge trigger, which comprises the following steps of: on the basis of the existing VLSI (Very Large Scale Integrated) DFT method designed by internal scan, using a double-edge scanning trigger to replace a single-edge scanning trigger in the gate-level netlist file with a built scan chain; adding a test clock circuit; simulating a test vector generated through the scan chain circuit of the single-edge scanning trigger by the scan chain circuit comprising the double-edge scanning trigger; and using the simulated test vector to test the scan chain circuit by an ATE (Automatic Test Equipment) device. In this way, the VLSI DFT method disclosed by the invention can be suitable for the circuit comprising the double-edge trigger and the circuit comprising the single-edge trigger, and further, the method is suitable for popularizing the double-edge trigger in the VLSI design and finally multiplying data handling capacity and reducing half of the power consumption of the integrated circuit.

Description

technical field [0001] The present application relates to a testability design method of a semiconductor integrated circuit, in particular to a testability design method of a semiconductor integrated circuit including a double-edge trigger. Background technique [0002] The manufacture of VLSI (Very Large Scale Integration) includes hundreds of processes, and slight changes in temperature and environment during the manufacturing process may cause physical defects in the chip, resulting in the chip not working properly. [0003] In order to ensure the quality of the manufactured chips, it is necessary to test and screen the produced chips. VLSI testing is divided into two categories: functional testing and structural testing. Functional test is a test for the function realized by the circuit, which should be solved in the design process. Structural testing is based on the structure of the circuit (gate type, connection, netlist, etc.), and observes the state of internal sig...

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Problems solved by technology

[0020] The above-mentioned design-for-test method using internal scan design cannot be applied to dual-edge triggers because:

[0021] First, in the second stage of logic synthesis, none of the current mainstream logic synthesis tools in the industry can handle double-edge triggers. Therefore, in the RTL-level circuit description file formed in the first step design input stage, only double-edge flip-flops can be changed. It is a single-edge trigger, so the test of double-edge trigger cannot be carried out according to the existing method

[0022] Its second, the 6th step generates test vector stage, although existing ATPG tool can generate ATPG test vector for double-edge trigger, but because the emulator that ATPG tool comes with can't correctly identify the test model of double-edge trigger, so can't Verify the generated test vectors

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