Multi-chip packaging structure and multi-chip packaging method

Abstract

The embodiment of the invention provides a multi-chip packaging structure and a multi-chip packaging method. n chips are sequentially stacked and arrayed on a chip loading platform; moreover, each chip partially covers the chip of the lower layer, so that a pad of the chip of the lower layer is exposed; a second bonding lead connects the pad on one chip to the pad on the other chip; and a first bonding lead connects the pad to a pin, accordingly, a minimum packaging area is obtained, moreover, the lengths of the first bonding lead and the second bonding lead are shortest, the powder loss which is caused by the self resistances of the bonding leads is lowered, and the reliability of the lead bonding is improved.

Description

technical field [0001] The invention relates to the field of integrated circuits, and more specifically relates to a multi-chip packaging structure and a packaging method thereof. Background technique [0002] In the semiconductor industry, the production of integrated circuits can be divided into three stages: integrated circuit design, integrated circuit manufacturing and integrated circuit packaging. In the manufacture of integrated circuits, chips are completed by the steps of wafer manufacturing, forming integrated circuits, and cutting wafers. After the integrated circuit inside the wafer is completed, a plurality of bonding pads are arranged on the wafer, so that chips formed by dicing the wafer can be electrically connected to a carrier externally through these bonding pads. The carrier is, for example, a lead frame or a package substrate. The chip can be connected to the carrier by wire bonding or flip-chip bonding, so that the pads of the chip can be electrically...

AI Technical Summary

Problems solved by technology

[0007] In view of this, the purpose of the present invention is to provide a novel power integrated circuit chip packaging s

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