Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a manufacturing method for a semiconductor structure. The method includes that silicon on insulator (SOI) substrates are provided, a gate structure is formed on the SOI substrates, SOI layers and buried oxide (BOX) layers of the SOI substrates on two sides of the gate structure are etched so as to form a groove exposing the BOX layers, the groove partially extends to the BOX layers, a metal side wall is formed on the side wall of the groove, the metal side wall is in contact with the SOI layers below the gate structure, an insulating layer which is used for filling partial groove is formed, a dielectric layer which is used for covering the gate structure and the insulating layer is formed, the dielectric layer is etched to form a first contact hole which at least exposes partial insulating layer, the insulating layer is etched through the first contact hole so as to form a second contact hole which exposes at least partial metal side wall, the first and the second contact holes are filled so as to form a contact plug, and the contact plug is in contact with the metal side wall. According to the method, the performance of the semiconductor device is improved, and the machining difficulty is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a manufacturing method thereof. Background technique [0002] With the development of semiconductor structure manufacturing technology, integrated circuits with higher performance and stronger functions require greater component density, and the size, size and space of each component, between components or each component itself need to be further reduced (currently can reach nanoscale), with the reduction of the size of semiconductor devices, various microscopic effects are highlighted. In order to meet the needs of device development, those skilled in the art have been actively exploring new manufacturing processes. [0003] Silicon-On-Insulator (SOI) has good dielectric isolation characteristics. Integrated circuits made of SOI have the advantages of small parasitic capacitance, high integration density, fast speed, simple process and sma...

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Problems solved by technology

[0005] The above-mentioned semiconductor structure has the following defects, such as figure 1 As shown, when etching the dielectric layer 17 to form the contact plug of the source / drain region in the subsequent process, it is necessary to align the source / drain region on the semiconductor layer 14 on the one hand, and to avoid damaging the gate structure 15 on the other hand. The corrosion control requirements are relatively high; for the semiconductor structure using the metal gate, there is a certain capacitance between the metal gate and the contact plug during the working process, which will affect the working performance of the semiconductor device; in the formation and source / drain When contacting the contact plug in the region, due to the reduction of the device size, the contact area between the bottom of the contact plug and the source / drain region is limited, so the contact resistance is relatively large, which will also affect the performance of the semiconductor device.

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