Semiconductor device structure and fabrication method of semiconductor device structure

Abstract

The invention discloses a semiconductor device structure which comprises a substrate, a plurality of P traps and a plurality of dielectric film areas, wherein an N-type epitaxy is grown on the substrate and provided with at least one P trench filled with P-type silicon; the P traps are arranged at the top end of the N-type epitaxy; the dielectric film areas are positioned above the P traps; surface metal is installed above the dielectric film areas; a contact hole is formed between every two dielectric film areas; each P trench is at least divided into two areas; all the areas are filled with the P-type silicon in different doping concentrations; a P-type film is realized by using a nonuniform impurity distribution mode; the bottom areas of the P trenches are filled with the P-type silicon with the doping concentrations less than or equal to the uniform doping concentration; and the top middle areas of the P trenches are filled with the P-type silicon with the doping concentrations greater than the uniform doping concentration. The invention further discloses a fabrication method of the device structure. The semiconductor device structure can improve current surge resistance of a device in the switch-off process under the condition that specific on resistance of the device is not affected.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a semiconductor device structure. The invention also relates to a manufacturing method of the semiconductor device structure. Background technique [0002] The device with super junction structure replaces the N drift region in the traditional VDMOS (vertical double diffused metal-oxide semiconductor field effect transistor) through the structure of P / N alternate arrangement, combined with the well-known VDMOS process in the industry, the MOSFET with super junction structure is produced (Metal-Oxide-Semiconductor-Field-Effect Transistor), which can greatly reduce the on-resistance of the device through the low-resistivity epitaxial layer under the condition that the reverse breakdown voltage is consistent with the traditional VDMOS. The carrier distribution of the P-type impurity and the carrier distribution of the N-type impurity in the P trench and...

AI Technical Summary

Problems solved by technology

The carrier distribution of the P-type impurity and the carrier distribution of the N-type impurity in the P trench and the matching of the carriers of the P-type impurity and the carriers of the N-type impurity will affect the characteristics of the device, and will affect the reverse direction of the device. Breakdown Voltage and Current Handling Capability

[0003] The general device design adopts alternating P / N films to achieve the best charge balance (the total amount of P-type carriers in the P-type thin layer is equal to the total amount of N-type carriers in the N-type thin layer) to obtain the device. The largest reverse breakdown voltage, N-type epitaxy is uniformly doped, to achieve the best charge matching, the corresponding P-type thin film has a uniform doping concentration of P0, and the current handling capacity of such devices is not enough

[0004] In order to improve the current handling capability of the device, there is a way to make the P-type impurity concentration adopt an uneven distribution in the direction perpendicular to the surface of the silicon wafer in the multiple epitaxy process. When the P-type film width is equal to the N-type When the width of the thin layer is thin, the characteristic is that the concentration of P-type impurities in the upper region is greater than that of the N region, and the concentration of P-type impurities in the lower region is smaller than that of the N region; in order to obtain more N-type regions to obtain lower Compared with the on-resistance, the width of the P-type film is smaller than the width of the N-type film. At this time, the concentration of the upper P-type impurity will be higher than the concentration of the N-type impurity; the concentration of the P-type impurity is higher than that of the adjacent N-type impurity, so that In the thermal process after the P / N film is formed, the P-type impurities diffuse more into the N film, causing the electrons in part of the N-type trench to be neutralized and affect the on-state resistance of the device. This effect is becomes more severe in trench MOSFETs

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