Built-in testing design method based on relevance model

A correlation model and test design technology, applied in the field of testability, can solve problems such as high product system complexity, design redundancy, and difficulty in assigning fault mode detection and isolation methods

Active Publication Date: 2013-02-13
CHINA AERO POLYTECH ESTAB
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Problems solved by technology

The parameter comparison method detects and isolates faults by comparing them with normal operating parameters. The parameter comparison method mainly relies on the engineering experience of the designer. Because there are many failure modes, strong correlations, and many characterization parameters of electronic equipment, the designer spends a lot of time determining the test parameters. Points, the relationship between monitoring parameters and faults, and the accuracy is not high; although the boundary scan method can isolate the fault to the device, it is only suitable for devices with boundary scan function, and it is difficult to perform boundary scan when the circuit is workin

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  • Built-in testing design method based on relevance model
  • Built-in testing design method based on relevance model
  • Built-in testing design method based on relevance model

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[0041] Example

[0042] The object selected in this case is the rotary transformer excitation generating circuit. This circuit is used to generate the sine signal required by the excitation winding of the resolver, and provide excitation for the operation of the resolver, so as to realize the detection requirements of the motor position in the control system of the aviation permanent magnet synchronous motor and the brushless DC motor. The functional block diagram of the circuit is as figure 1 Shown.

[0043] Based on the functional structure of the resolver excitation circuit, the test modeling software is used to test the circuit, and the correlation model is obtained as figure 2 As shown, the testability model includes a total of six functional modules: power supply module, sinusoidal signal generation, frequency control command digital-to-analog conversion, frequency control command output module, amplitude adjustment module, and drive capacity adjustment module. There are a ...

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Abstract

The invention belongs to the testability technology and relates to a built-in testing design method based on a relevance model. The method uses a product relevance model as a basis and comprises the following steps of: at first, simplifying the relevance model, and removing a redundancy test and combining an ambiguity group; secondly, identifying a minimum test vector matrix corresponding to each fault; thirdly, determining an optimal testing vector according to a reliability index and a test cost of a test as a criterion for fault detection and separation; and finally, converting the criterion into an embedded diagnostic program and arranging the embedded diagnostic program in a built-in test of a product. With the adoption of the method provided by the invention, a fault source can be accurately found out through the optimal test cost and the least test quantity, so that the testability and the design level of an electronic product can be improved.

Description

technical field [0001] The invention belongs to testing technology and relates to an in-machine test design method based on a correlation model. Background technique [0002] With the development and application of large-scale integrated circuits, the integration of electronic equipment is getting higher and higher, and the functions are becoming more and more complex, followed by the diversification of failure modes, which reflect strong coupling and correlation. When one type of fault occurs, it will cause multiple faults to occur at the same time, resulting in long and difficult fault detection and isolation time, and a rapid increase in maintenance workload. [0003] Built-in test (Built-in test, BIT) technology is the comprehensive ability of the system or equipment to rely on its internal detection circuit and detection software to complete system or equipment working parameter monitoring, fault detection and isolation. [0004] The existing BIT engineering design met...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 李璠蒋觉义刘萌萌曾照洋
Owner CHINA AERO POLYTECH ESTAB
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