Wafer level packaging structure with large contact area and preparation method thereof

Abstract

The present invention relates to a package for semiconductor device and the fabrication method for integrally encapsulating a whole semiconductor chip within a molding compound. In the semicondcutor device package, bonding pads distributed on the top of the chip are redistributed into an array of redistributed bonding pads located in an dielectric layer by utilizing the redistribution technique. The electrodes or signal terminals on the top of the semiconductor chip are connected to an electrode metal segment on the bottom of the chip by conductive materials filled in through holes formed in a silicon substrate of a semiconductor wafer. Furthermore, the top molding portion and the bottom molding portion seal the semiconductor chip completely, thus providing optimum mechanical and electrical protections.

Description

technical field [0001] The present invention generally relates to a method for preparing a wafer-level package. More specifically, the present invention aims to provide a wafer-level package structure and a preparation method with a relatively large soldering contact surface. Background technique [0002] Wafer Level Chip Scale Packaging (WLCSP) is a kind of IC packaging method. After the whole wafer is produced, the packaging test and ball planting are directly performed on the wafer, and then it is cut and made. For a single IC, the size of the chip that completes the packaging process is almost equal to the size of the original die. Among them, the solder balls or solder bumps planted on the wafer-level chip are used as the contact terminals for the electrical connection between the chip and the external circuit. As we all know, the power consumption of power devices is very large, and the solder balls or solder bumps are usually directly Soldered on the pads on the PCB ...

AI Technical Summary

Problems solved by technology

Among them, the solder balls or solder bumps planted on the wafer-level chip are used as the contact terminals for the electrical connection between the chip and the external circuit. As we all know, the power consumption of power devices is very large, and the solder balls or solder bumps are usually directly Soldered on the pads on the PCB printed circuit board, usually the volume of the solder balls or solder bumps is relatively small and their contact surface with the outside world is also very limited, which makes them easy to cause high impedance (High impedance) and Low thermal conductance effect

In addition, the exposed chip in the wafer-level chip size package not only lacks physical protection, which makes the chip easily damaged during transportation or various process preparation processes, but also such chips that are not resistant to moisture are also likely to reduce their service life

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