Method for designing high reliability and embedded type minimum central processing unit (CPU) core applicable to aerospace field and based on field programmable gate array (FPGA)

A CPU core and reliability technology, applied in the direction of machine execution devices, etc., can solve problems such as limited resources, achieve cost savings, high program reliability, and reduce component costs

Active Publication Date: 2013-02-20
SHANGHAI SPACEFLIGHT INST OF TT&C & TELECOMM
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The problem to be solved by the present invention is to provide a high-reliability embedded minimum CPU core design method based on FPGA, which can solve the problem of limited resources applicable to FPGA in the aerospace field, and can increase the reliability of spacecraft

Method used

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  • Method for designing high reliability and embedded type minimum central processing unit (CPU) core applicable to aerospace field and based on field programmable gate array (FPGA)
  • Method for designing high reliability and embedded type minimum central processing unit (CPU) core applicable to aerospace field and based on field programmable gate array (FPGA)
  • Method for designing high reliability and embedded type minimum central processing unit (CPU) core applicable to aerospace field and based on field programmable gate array (FPGA)

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specific Embodiment

[0033] This embodiment adopts C language to write a section program (a simple 1553B communication program), according to figure 2 The analysis of the instructions and target source uses the imitation assembly language to convert the C language program into Binary format machine code, and writes it into the PROM, and according to the CPU core designed in the FPGA software, disassemble the instruction and target source of the injected code points, identify the instruction type and target source, and then perform data read and write operations. The concrete steps of its method are as follows:

[0034] The C language program is as follows:

[0035]

[0036]

[0037] Step a1: According to figure 2 According to the analysis of the instructions and the target source, the program is written in imitation assembly language according to the C language program. This step is an important step in the entire design. This step is the source of the entire data. The code after writin...

Embodiment

[0053] Taking a certain model as an example, the architecture of FPGA+SCM+off-chip RAM+off-chip PROM was originally adopted, and the code was written in C language program. Now use the same program, write new code with imitation assembly language, compile and link, generate Binary format code, and write it into off-chip PROM, the original program function works well.

[0054] As can be seen from the above, adopting the method of the present invention to design the FPGA embedded CPU core in the aerospace field is a low price, increases the reliability of aerospace components, and can save a lot of financial and material resources.

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Abstract

The invention discloses a method for designing a high reliability and embedded type minimum central processing unit (CPU) core which is applicable to the aerospace field and based on field programmable gate array (FPGA). The method includes writing a program by a simulated assembly language in advance, converting the program to a machine code in a Binary mode, writing the machine code into a programmable read only memory (PROM), reading data in the PROM according to the program, subjecting the read data to a separation of instructions and target sources, identifying the types of the instructions and the target sources, performing arithmetic logic operation of the data, placing an operation result into a designated place, and finally performing read-write operation of external data according to the instructions. Compared with methods in the prior art, the method has the advantages that small FPGA resources are utilized, the resource spending of the core is over ten times lower than that of existing 80C51 core, the method is particularly applicable to the condition that FPGA resources are limited in the aerospace field, the engineering application effect is good, the read-write for the data can be externally performed, the communication between 422 and 1553B can be achieved, the program is written by the simulated assembly language, and the program reliability is high.

Description

technical field [0001] The invention relates to software in the field of FPGA-based embedded CPU cores, and is especially suitable for the technical requirements of small resources and high reliability of aerospace FPGAs. Background technique [0002] Due to the particularity of its working place in the aerospace field, the quality and reliability of products are extremely high, and no failure is allowed. In space, due to the impact of high-energy particles and continuous irradiation, the level of components is extremely high. Due to its own process design, the available resources of FPGAs that can go to the sky are currently limited, and the use of 80C51 cores takes up too many resources and cannot be applied. [0003] At present, most of the missions in the aerospace field adopt the system architecture of FPGA + MCU + off-chip RAM + off-chip PROM. Sex will decrease. Contents of the invention [0004] The problem to be solved by the present invention is to provide a hi...

Claims

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Application Information

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IPC IPC(8): G06F9/30
Inventor 施未勋徐建萍周振宇宋晓东
Owner SHANGHAI SPACEFLIGHT INST OF TT&C & TELECOMM
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