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Semiconductor packaging structure and method of fabricating same

A packaging structure and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as excessive thickness and poor reliability, and achieve improved reliability and good electrical performance Transmission efficiency, the effect of saving high material costs

Active Publication Date: 2013-03-06
UNIMICRON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In view of the various deficiencies of the above-mentioned prior art, the main purpose of the present invention is to provide a semiconductor packaging structure and its manufacturing method, which can effectively improve the problems of excessive thickness and poor reliability of the existing semiconductor packaging structure.

Method used

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  • Semiconductor packaging structure and method of fabricating same
  • Semiconductor packaging structure and method of fabricating same
  • Semiconductor packaging structure and method of fabricating same

Examples

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no. 1 example

[0063] Generally speaking, the implementation of the present invention can be divided into three stages, at first, prepare a plurality of semiconductor chips such as dynamic random access memory (DRAM), please refer to Figure 2A to Figure 2C , is a cross-sectional view of the semiconductor chip of the semiconductor package structure of the present invention and its manufacturing method.

[0064] Such as Figure 2A As shown, a semiconductor wafer 20 having an opposite active surface 20 a and a non-active surface 20 b, and a plurality of electrode pads 21 and buffer layers 22 formed on the active surface 20 a are provided.

[0065] Such as Figure 2B As shown, a metal bump 23 is formed on each of the electrode pads 21 .

[0066] Such as Figure 2C As shown, the semiconductor wafer 20 is thinned from the non-active surface 20b, and the semiconductor wafer 20 is cut to obtain a plurality of semiconductor chips 20', each of which has an opposite active surface 20a' and a non-ac...

no. 2 example

[0085] Generally speaking, the main difference between this embodiment and the first embodiment is only the implementation of the metal foil, please refer to Figure 5A to Figure 5C , which is a cross-sectional view of the second embodiment of the metal foil 50' of the semiconductor package structure of the present invention and its manufacturing method.

[0086] Such as Figure 5A As shown, a metal plate 50 is provided, and the material of the metal plate 50 can be copper or other metals.

[0087] Such as Figure 5B As shown, a plurality of punched bumps 51 are formed on the metal plate 50 by punching.

[0088] Such as Figure 5C As shown, the third adhesive layer 32 covering each of the stamped bumps 51 is formed on the metal plate 50 , and then, the third adhesive layer 32 can be solidified in a B-stage according to circumstances.

[0089] Next, carry out assembly and packaging operations, please refer to Figure 6A to Figure 6I , which is a cross-sectional view of the...

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Abstract

The present invention relates to a semiconductor packaging structure and a method for fabricating the same. The semiconductor packaging structure includes a semiconductor chip, a packaging layer, a dielectric layer, a wiring layer, and a metallic foil. The semiconductor chip has an active surface, an inactive surface opposing the active surface, electrode pads formed on the active surface, and metal bumps formed on the electrode pads. The packaging layer encapsulates the semiconductor chip and exposes the active surface. The dielectric layer is formed on the active surface and a surface of the packaging layer at the same side with the active surface, and has wiring pattern openings for the metal bumps to be exposed therefrom. The wiring layer is formed in the wiring pattern openings. The metallic foil is disposed on the packaging layer adjacent to the inactive surface. Metallic protrusions are formed on the metallic foil, and penetrate the packaging layer to extend to the inactive surface of the semiconductor chip. The Semiconductor packaging structure and the method of fabricating the same can effectively improve the problems that the prior semiconductor packaging structure is too thick and is bad in reliability.

Description

technical field [0001] The invention relates to a semiconductor packaging structure and a manufacturing method thereof, in particular to a semiconductor packaging structure embedded with a semiconductor chip and a manufacturing method thereof. Background technique [0002] With the vigorous development of the electronic industry, electronic products tend to be thinner and shorter in shape, but still need to comply with the specifications of the Joint Electronic Device Engineering Council (JEDEC) specifications, so the packaging method is very important. For example, due to the development of Dynamic Random Access Memory (DRAM) chips below 40 nanometers (nm), the chip size is getting smaller and smaller, but the packaged area still needs to be the same, so that the packaging structure can be used for placement. The ball pitch of the circuit board (PCB) is maintained at 0.8 millimeters (mm) to comply with the JEDEC standard, so fan-out chip size packaging is one of the availab...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/485H01L23/367H01L21/60H01L21/48
CPCH01L23/36H01L24/97H01L2924/01029H01L2224/4824H01L23/3677H01L2224/45144H01L23/5389H01L2924/12042H01L24/19H01L24/96H01L2224/214H01L2224/04105H01L2224/12105H01L2224/73267H01L2924/15159H01L2924/00015H01L2924/00
Inventor 胡迪群胡玉山
Owner UNIMICRON TECH CORP
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