Diode chip manufacturing method
A diode and chip technology, which is applied in the field of diode chip preparation, can solve the problems affecting the working performance of the chip and the heat of the chip, and achieve the effect of improving the breakdown voltage and protecting the chip.
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Embodiment 1
[0038] A method for preparing a diode chip, comprising an N+ layer and a P+ layer, characterized in that, the steps are as follows:
[0039] A), growing at least one N-type layer for current drift on the front side of the N+-type substrate silicon wafer;
[0040] B), growing a layer of silicon dioxide on the surface of the N-type layer;
[0041] C), coating photoresist on the silicon dioxide layer;
[0042] D), photoetching the pressure divider ring window and the main junction window on the photoresist, and etching the groove;
[0043] E), after the above step D), use the ion implantation method to generate P+ layer and P- layer, forming a closed ring with P+ layer as the main junction and at least one pressure dividing ring P- layer as the secondary junction;
[0044] F) Coating a glass passivation layer on the etched groove;
[0045] G), sputtering a nickel alloy layer on the surface of both the N+ layer and the P+ layer.
Embodiment 2
[0047] A method for preparing a diode chip, comprising an N+ layer and a P+ layer, characterized in that, the steps are as follows:
[0048] A), growing at least one N-type layer for current drift on the front side of the N+-type substrate silicon wafer;
[0049] B), growing a layer of silicon dioxide on the surface of the N-type layer;
[0050] C), coating photoresist on the silicon dioxide layer;
[0051] D), photoetching the pressure divider ring window and the main junction window on the photoresist, and etching the groove;
[0052] E), after the above step D), use the ion implantation method to generate P+ layer and P- layer, forming a closed ring with P+ layer as the main junction and at least one pressure dividing ring P- layer as the secondary junction;
[0053] F) Coating a glass passivation layer on the etched groove;
[0054] G), sputtering a nickel alloy layer on the surface of both the N+ layer and the P+ layer.
[0055] The photoresist coated in step C)...
Embodiment 3
[0057] A method for preparing a diode chip, comprising an N+ layer and a P+ layer, characterized in that, the steps are as follows:
[0058] A), growing at least one N-type layer for current drift on the front side of the N+-type substrate silicon wafer;
[0059] B), growing a layer of silicon dioxide on the surface of the N-type layer;
[0060] C), coating photoresist on the silicon dioxide layer;
[0061] D), photoetching the pressure divider ring window and the main junction window on the photoresist, and etching the groove;
[0062] E), after the above step D), use the ion implantation method to generate P+ layer and P- layer, forming a closed ring with P+ layer as the main junction and at least one pressure dividing ring P- layer as the secondary junction;
[0063] F) Coating a glass passivation layer on the etched groove;
[0064] G), sputtering a nickel alloy layer on the surface of both the N+ layer and the P+ layer.
[0065]The photoresist coated in step C) ...
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