Method for manufacturing metal silicide thin film and ultra-shallow junction and semiconductor device

[0021] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, a person of ordinary skill in the art can understand that in each embodiment of the present invention, many technical details are proposed for the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed by the claims of this application can be realized.

[0022] The first embodiment of the present invention relates to a method for manufacturing a metal silicide film and an ultra-shallow junction. The specific process is as follows figure 1 As shown, it includes the following steps:

[0023] Step 101, provide a semiconductor substrate 201, such as Figure 2A As shown; the semiconductor substrate can be silicon (Si), germanium (Ge), silicon germanium (SiGe), III-V semiconductor. A gate structure 202 is formed on the semiconductor substrate, which includes a gate dielectric layer, a gate electrode, and a protective layer on its sidewalls. The method of forming the gate structure is consistent with the prior art, and will not be repeated here.

[0024] Step 102, using a mixture of metal and semiconductor doped impurities as a target, and using a physical vapor deposition PVD method to deposit a thin film of the mixture on the semiconductor substrate, such as Figure 2B As shown, 203 is a mixed film.

[0025] Physical vapor deposition (PVD) is a well-known technique used in integrated circuit manufacturing. During PVD, the required coating material is used as a spray target and deposited on the substrate. Such as image 3 Shown is a schematic diagram of the PVD cavity. The target 301 and the semiconductor substrate 201 on which the gate structure 202 is formed are placed in a vacuum chamber 300, which is evacuated and maintained at a very low pressure (for example, less than 10 mtorr).

[0026] The vacuum chamber 300 is filled with an inert gas 303, such as argon, and the required gas pressure in the chamber is maintained by a pumping system (not shown in the figure). Using conventional methods, a glow discharge plasma is generated in a low-pressure gas, and at least part of the gas is ionized. If the target is properly biased, the positive ions in the plasma can be accelerated toward the target, causing the target 305 to be ejected from the target electrode. Part of the sprayed target is deposited on the semiconductor substrate 201 to form a mixture film 203.

[0027] In this embodiment, the target material is a metal-rich mixture and exists in the form of a polycrystalline solid material. The mixture can be obtained by mixing metal powder and semiconductor impurity-doped powder and through heat treatment or other treatments. The semiconductor doped impurities in the target are evenly distributed in the metal. Wherein, the content of semiconductor doping impurities in the mixture of metal and semiconductor doping impurities is between 0.1% and 5%. The metal may be any one of nickel (Ni), platinum (Pt), platinum (Pt), titanium (Ti), cobalt (Co), molybdenum (Mo) or an alloy formed by any combination thereof. For most applications, nickel is preferred. Nickel is usually Pt, W or other combinations of the above metals to facilitate stability and adjustment of Schottky barrier height. Semiconductor doping impurities can be P-type doped boron (B), boron fluoride (BF 2 ), any one or any combination of indium (Indium); or any one or any combination of N-type doped phosphorus (P) and arsenic (As).

[0028] Although the target is a mixture of metal and semiconductor doped impurities, the process flow of the PVD method is consistent with the prior art, and will not be repeated here. After the mixture film is deposited, metal ions and semiconductor doped impurity ions will penetrate into the semiconductor substrate, forming an ultra-shallow ion diffusion zone in the semiconductor substrate, such as Figure 2C Shown in 204. Specifically, the metal in the mixture film 203 will react with the semiconductor substrate to form a metal silicide, and the semiconductor dopant impurities in the mixture film 203 will diffuse into the metal silicide, the interface between the metal silicide and the semiconductor substrate, and ion diffusion. The interface between the region and the semiconductor substrate and the diffusion in the semiconductor substrate form an ion diffusion region 204.

[0029] Step 103, wet removing the mixture film, such as Figure 2D Shown. In this step, a conventional wet etching technique can be used to remove the remaining mixture film on the surface of the semiconductor substrate, which will not be repeated here.

[0030] Step 104, annealing the semiconductor substrate on which the mixture film has been deposited and removed, to form a metal silicide film and an ultra-shallow junction, such as Figure 2E As shown, 205 and 207 are metal silicide contact regions of the source or drain, and 206 and 208 are impurity diffusion regions of the source or drain. Generally, a PN junction is formed between the impurity diffusion regions 206 and 208 and the semiconductor substrate, and an ohmic contact is formed between the metal silicide 205/207 and the impurity diffusion region 206/208. However, when the formed impurity diffusion regions 206 and 208 are sufficiently small (for example, less than 1.5 nanometers), a metal-semiconductor contact is formed between the metal silicide and the semiconductor substrate.

[0031] In this step, conventional rapid thermal annealing (RTP) can be used for annealing, or microwave heating can be used for annealing. The process flow is similar to the conventional annealing process, and metal silicide and super shallow are formed at a relatively low temperature. Junction, so that the metal silicide can exist stably. In addition, the substrate temperature when depositing the compound thin film on the semiconductor substrate may be between 0 and 300°C. Depending on the formation temperature of different metal silicides and the highest temperature for stable existence, the annealing temperature can be between 300 and 800°C. In step 102, the metal and semiconductor dopant impurities diffuse into the semiconductor substrate to form a metal silicide; and the semiconductor dopant impurities contained in the metal silicide will continue to diffuse into the semiconductor substrate during annealing to form an ultra-shallow junction . Due to the low formation temperature and stable existence temperature of metal silicide, such as nickel silicide (NiSi), cobalt silicide (CoSi) 2 ), titanium silicide (TiSi 2 The stable existence temperature of) is less than 600, 700, and 1000°C respectively. Therefore, when metal silicide and ultra-shallow junction are formed at a relatively low temperature, the semiconductor dopant impurities may not be fully activated in the semiconductor substrate, but , If it can be fully activated, it will form a PN junction; if it cannot be fully activated, it can also form a metal semiconductor junction; that is, in the process of forming ultra-shallow junctions and ultra-thin metal silicides, the formation of ultra-shallow junctions It can be a PN junction or a metal semiconductor junction.

[0032] The ultra-shallow junction and metal silicide films formed by the above steps can be used in ultra-shallow junction semiconductor field effect transistors. The thickness of the metal silicide is about 3 to 12 nanometers, and the junction depth is about 1 to 15 nanometers. The peak doping concentration in the source/drain region of the ultra-shallow junction is about 2×10 per cubic centimeter 19 To 2×10 20 Each ion, the length of the gate structure is about 7 to 25 nanometers.

[0033] In addition, it is worth mentioning that by using microwave heating annealing technology, metal silicide and ultra-shallow junction can be formed at a relatively low temperature, so that the metal silicide can exist stably. In addition, the ability of different materials on the substrate to absorb microwave energy is different, and microwave heating is closely related to defects in the substrate. The damage to the semiconductor crystal lattice caused by impurities or other factors can be regarded as defects. The more, the greater the microwave heating effect, that is, defects can enhance the ability of microwave absorption. Aiming at this feature, the use of microwave heating for annealing can improve the heating efficiency.

[0034] In addition, it is worth noting that because the mixed film contains metal and semiconductor doped impurities, when microwave heating and annealing are performed, the cavity of the microwave heating equipment needs to contain multi-mode and multi-frequency electromagnetic waves during heating. The center frequency is between 1.5GHz and 15GHz, so that the material to be heated is fully heated. In addition, it is worth noting that when microwave heating is performed, the microwave electromagnetic waves used by the microwave heating equipment have a Gaussian distribution around 5.8GHz, and can be heated at intervals of 30Hz-50Hz with multiple frequencies. At the same time, these different frequencies of microwaves in the cavity At the same time, it has the feature of multi-mode, which can ensure the uniformity and consistency of microwave energy distribution inside the cavity, and further lead to uniformity and consistency when heating the substrate.

[0035] Compared with the prior art, this embodiment adopts a mixture of metal and semiconductor doped impurities as a target, physical vapor deposition PVD method deposits the mixture film on the semiconductor substrate, wet removal of the mixture film, and annealing to form Extremely ultra-thin uniform metal silicide film and ultra-shallow junction. Since the mixture of metal and semiconductor doped impurities is used as the target to deposit the mixture film, and the mixture film is wet removed before the heating and annealing, the self-limiting limit ultra-thin uniform metal can be simultaneously formed in the semiconductor field effect transistor manufacturing process Silicide films and ultra-shallow junctions can be used in field effect transistors at 14nm, 11nm and below technology nodes.

[0036] The second embodiment of the present invention relates to a manufacturing method of a metal silicide film and an ultra-shallow junction. The second embodiment is further improved on the basis of the first embodiment. The main improvement lies in: in the second embodiment of the present invention, before annealing, at least two deposition and wet removal of the mixture film are performed; also That is to say, before annealing, the mixture film deposition and wet removal are performed many times, and the thickness of the metal silicide film and the ultra-shallow junction can be limited by the number of repeated executions, and the final metal silicide film and Super shallow knots are more uniform.

[0037] In addition, in the process of repeating the deposition and wet removal of the mixture thin film, each time the mixture thin film is deposited, a mixture of different metals and semiconductor doped impurities can be used as the target. For example, in the deposition of a mixture film, the first time is a mixture of platinum and boron, the second time is a mixture of nickel and boron, or a mixture of nickel and indium; that is, you can choose according to actual needs Metals are used to prepare metal silicides, which can expand the selection range of metals that can be used when forming metal silicides, so that the resistance of the metal silicides is as small as possible, and the application is more flexible.

[0038] The third embodiment of the present invention relates to a manufacturing method of a metal silicide film and an ultra-shallow junction. The third embodiment is further improved on the basis of the first embodiment or the second embodiment. The main improvement lies in: in the third embodiment of the present invention, an improved high-power pulsed magnetron sputtering technology (HiPIMS) is adopted. PVD deposition is carried out by ionizing the target material and depositing the mixture film by applying a substrate bias on the semiconductor substrate. On the one hand, metal ions and semiconductor impurity ions can be deposited at a certain acceleration The surface of the semiconductor substrate controls the diffusion depth of ions; on the other hand, it can improve the uniformity and stability of film deposition on the three-dimensional structure.

[0039] Specifically, in the process of using a mixture of metal and semiconductor doped impurities as the target material, and using the physical vapor deposition PVD method to deposit the mixture film on the semiconductor substrate, the target material is ionized into an ion state to produce metal ions Doping impurity ions with the semiconductor, and applying a substrate bias on the semiconductor substrate. Among them, ionizing the target material into an ion state is achieved by applying a first bias voltage to the target material.

[0040] In addition, the first bias voltage may be any of a direct current bias voltage, an alternating current bias voltage or a pulsed bias voltage. The magnitude of the first bias voltage depends on the PVD system used, that is, the magnitude of the first bias voltage varies accordingly when the PVD system is different; generally speaking, the magnitude of the first bias voltage is 200V~1000V. For bias and pulse bias, the above-mentioned magnitude refers to its effective value. In addition, the substrate bias is any one of DC bias, AC bias, or pulse bias. The size of the substrate bias voltage is adjustable. By adjusting the size of the substrate bias voltage, the amount of metal ions diffused to the surface of the semiconductor substrate can be adjusted, so that the thickness of the finally formed metal semiconductor compound film can be adjusted. Generally speaking, the magnitude of the substrate bias voltage is 200V˜1000V, and for the AC bias voltage and the pulse bias voltage, the aforementioned magnitude refers to its effective value.

[0041] The fourth embodiment of the present invention relates to a semiconductor device, such as Figure 2E As shown, it includes: a metal silicide film and an ultra-shallow junction. The metal silicide film and the ultra-shallow junction use a mixture of metal and semiconductor doped impurities as a target, and the mixture is deposited on a semiconductor substrate by a physical vapor deposition PVD method The thin film is formed by wet removal of the mixed thin film and annealing; among them, the super shallow junction is a PN junction or a metal semiconductor junction.

[0042] Since the mixture of metal and semiconductor doped impurities is used as the target to deposit the mixture film, and the mixture film is wet removed before the heating and annealing, the self-limiting limit ultra-thin uniform metal can be simultaneously formed in the semiconductor field effect transistor manufacturing process Silicide films and ultra-shallow junctions can be used in field effect transistors at 14nm, 11nm and below technology nodes. For example, the thickness of the metal silicide is about 3 to 12 nanometers, the junction depth is about 1 to 15 nanometers, and the peak doping concentration in the source/drain regions of the ultra-shallow junction is about 2× per cubic centimeter 10 19 To 2×10 20 Each ion, the length of the gate structure is about 7 to 25 nanometers.

[0043] It should be noted that the content of semiconductor doping impurities in the mixture of metal and semiconductor doping impurities is between 0.1% and 5%. The metal may be any one of nickel (Ni), platinum (Pt), platinum (Pt), titanium (Ti), cobalt (Co), molybdenum (Mo), or an alloy formed by any combination thereof. For most applications, nickel is preferred. Nickel is usually combined with Pt, W or other metals mentioned above to facilitate stability and adjustment of Schottky barrier height. Semiconductor doping impurities can be P-type doped boron (B), boron fluoride (BF 2 ), any one or any combination of indium (Indium); or any one or any combination of N-type doped phosphorus (P) and arsenic (As).

[0044] It is not difficult to find that this embodiment is a system example corresponding to the first embodiment, and this embodiment can be implemented in cooperation with the first embodiment. The related technical details mentioned in the first embodiment are still valid in this embodiment, and in order to reduce repetition, they will not be repeated here. Correspondingly, the related technical details mentioned in this embodiment can also be applied in the first embodiment.

[0045] Those of ordinary skill in the art can understand that the above-mentioned embodiments are specific examples for realizing the present invention, and in actual applications, various changes can be made in form and details without departing from the spirit and spirit of the present invention. range.