Multi--core processor oriented on-chip lock variable global addressing storage method and device

Abstract

The invention discloses a multi--core processor oriented on-chip lock variable global addressing storage method and a device. The method comprises the following steps: 1, a global addressing on-chip lock memory is established in advance; a lock variable is marked in the process of constructing an application, and the lock variable is allocated to an exclusive address space during compiling and linking; 2, in the process of loading the application, the page in which the lock variable is allocated is transferred to the global addressing on-chip lock memory through the DMA (direct memory access) mode; an access request is arbitrated and added to an access queue when the application accesses the lock variable, and the access request is executed according to the first-come-first-served strategy; the mapping of the lock variable is terminated when the application ends; and the device comprises a memory bank and an access controller, wherein the memory bank is arranged on a multi--core processor chip and used for storing the lock variable of the application, and the access controller is used for controlling the reading and modification towards the lock variable when the application runs. The multi--core processor oriented on-chip lock variable global addressing storage method and the device have the advantages that the concurrent access performance of the lock variable is high, the access delay of the lock variable is low, the concurrent access overhead of the lock variable is low, and the storage method and the device are simple and convenient in use.

Description

technical field [0001] The invention relates to the field of architecture design of shared storage many-core processors, in particular to an on-chip lock variable global addressing storage method and device for many-core processors. Background technique [0002] 1) Shared memory on-chip many-core processor [0003] Over the past 30 years, with the advancement of integrated circuit implementation technology, the number of transistors on a high-performance general-purpose microprocessor chip has been obeying Moore's law and nearly doubling every 18 months or so. The number of transistors on the current mainstream high-end processor chips has reached the order of 1 billion. How to use such a large number of transistor resources to design and implement high-performance general-purpose microprocessors is a common concern in the academic and industrial circles. The many-core processor architecture on a chip that shares multi-level storage levels is the mainstream architecture of...

AI Technical Summary

Problems solved by technology

This will cause a large number of L1 level cache invalidation operations when many threads read and write lock variables concurrently, reducing the performance of high-concurrency applications

[0006] 2) To treat the lock variable as a general data variable, it is necessary to manage the virtual memory page where the lock variable is located according to a unified virtual memory management mechanism. Then, the virtual memory page where the lock variable is located is likely to be swapped out of the main processor Memory, which affects the performance of concurrent access to lock variables by high-concurrency applications

Moreover, due to the same storage management method as ordinary data, access to lock variables also undergoes the same virtual-real address conversion process as data variables, which will greatly reduce performance when many threads access lock variables concurrently.

[0007] 2) Lock variable access is an important factor restricting performance improvement in a high concurrency environment

However, this technical solution is not suitable for the processor architecture of many cores on a chip. At the same time, the patent does not map the lock variable memory into the global address space, so complex virtual and real address conversion is required when accessing the lock variable. Variable access performance is low

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