Dynamic comparator with large offset voltage correction range

A dynamic comparator, offset voltage technique used in improving amplifiers to reduce temperature/supply voltage variations, etc.

Inactive Publication Date: 2013-04-10
SHENZHEN GRADUATE SCHOOL TSINGHUA UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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  • Dynamic comparator with large offset voltage correction range
  • Dynamic comparator with large offset voltage correction range
  • Dynamic comparator with large offset voltage correction range

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[0026] Referring to the accompanying drawings, the embodiments of the dynamic comparator with a large offset voltage correction range will be described in detail below. It should be emphasized that the following description is only exemplary and not intended to limit the scope of the invention and its application.

[0027] Figure 4 It is the schematic diagram of the dynamic comparator proposed by the present invention. The dynamic comparator consists of a pre-amplifier, a latch and an offset correction circuit based on successive approximation logic.

[0028]In the pre-amplifier, the NMOS transistor MN0 is a bias current source, and its gate is connected to an externally provided clock signal CLK. The MN1 and MN2 tubes are differential input pair tubes and are also NMOS tubes. Their gates receive the compared signals respectively. When the comparator is corrected, the two input ports are short-circuited. The PMOS transistors MP5 and MP6 are load MOS transistors, and their ...

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Abstract

The invention discloses a dynamic comparator with a large offset voltage correction range. The dynamic comparator comprises a pre-amplifier, a latch and an offset correction circuit based on successive approximation logic; the dynamic comparator is characterized in that a cascade MOS (metal-oxide semiconductor) pipe is inserted between a loaded MOS pipe drain electrode and an output node of a pre-amplified circuit; capacitor arrays used for correcting the offset voltage are connected with the drain electrode (namely the output node of the pre-amplifier) and the source electrode of the cascade MOS pipe. As the cascade pipe has a transformation function to the source impedance of the cascade pipe, the capacitor array connected with the drain electrode of the cascade pipe has a large correction range for the offset voltage of the comparator, the capacitor array connected with the source electrode of the cascade pipe can reduce the corrected residual offset voltage of the comparator, and the ratio value of the maximum capacitance and the minimum capacitance in the capacitor arrays of the drain electrode and the source electrode is always realized easily, and moreover, the capacitor arrays have higher matching degrees.

Description

technical field [0001] The invention relates to the field of analog circuit design, in particular to a dynamic comparator with a large offset voltage correction range. Background technique [0002] Dynamic comparators consume less power because they do not consume static power. Dynamic comparators generally use latches to speed up the signal comparison process, so they are fast. Dynamic comparators typically use small form factor devices and therefore small area. But on the other hand, the offset and noise of the dynamic comparator are relatively large, which limits its application in high-precision circuits. [0003] A latch-based dynamic comparator generally includes a two-stage circuit of a pre-amplifier and a latch. In order to correct the offset voltage of the comparator, the method of paralleling the adjustable capacitor array at the output node of the pre-amplifier can be used, such as figure 1 shown. In the process of offset voltage correction, the output QP and...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03F1/30
Inventor 王自强姜珲张春麦宋平陈虹王志华
Owner SHENZHEN GRADUATE SCHOOL TSINGHUA UNIV
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