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Programmable precise clock circuit based on field programmable gate array (FPGA)

A precise clock and circuit technology, applied in the direction of logic circuits using specific components, logic circuits using basic logic circuit components, etc., can solve problems such as increasing device costs, hindering high chip integration, and difficulty in integrating chips, so as to improve integration Degree, cost reduction, and the effect of saving FPGA resources

Active Publication Date: 2013-04-10
无锡南理工新能源电动车科技发展有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Usually digital systems use off-chip quartz crystal oscillators to obtain clock source signals. Quartz crystal oscillators have superior voltage and temperature characteristics and can work stably, but they are difficult to integrate into the chip and increase the cost of the device, hindering the high integration of the chip change

Method used

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  • Programmable precise clock circuit based on field programmable gate array (FPGA)
  • Programmable precise clock circuit based on field programmable gate array (FPGA)
  • Programmable precise clock circuit based on field programmable gate array (FPGA)

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Embodiment Construction

[0016] An FPGA-based programmable precise clock circuit of the present invention includes an oscillating unit and a programmable delay unit. The described oscillating unit is composed of 2 D flip-flops and 2 NOT gates to realize the inversion of the output clock signal; the described The programmable delay unit is composed of several selectors and basic delay units, and uses layout and wiring constraint technology to make the clock cycle precise and controllable.

[0017] The described basic delay unit is realized by the look-up table of FPGA, which can delay a fixed time. Nanosecond-level precise delay can be realized.

[0018] The described two-choice selector NAND gate is realized by the look-up table of FPGA, so as to realize the minimum delay time of the system.

[0019] The described programmable delay unit is composed of a number of selectors and a basic delay unit. The selector selects whether to pass through the basic delay unit, and can output clock signals of diffe...

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PUM

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Abstract

The invention discloses a programmable precise clock circuit based on field programmable gate array (FPGA). The programmable precise clock circuit based on the FPGA is composed of an oscillating unit and a programmable delay unit. The oscillating unit is composed of two D-flip flops and two not-gates and is used for achieving turning-over of an output clock signal. The programmable delay unit is composed of a plurality of alternative selectors and a basic delay unit in a cascading mode. Period of the clock is enabled to be precise and controllable by adopting a locating and wiring restraining technique. According to the programmable precise clock circuit based on the FPGA, a clock up to Ghz-frequency range is achieved. Due to the fact that the FPGA is adopted, the programmable precise clock circuit based on the FPGA is high in precision, and strong in generality and applicability.

Description

technical field [0001] The invention belongs to a clock circuit, in particular to a FPGA-based programmable precise clock circuit. Background technique [0002] The clock source is the key to the realization of electronic systems such as radar, communication, and test instruments. The realization of many modern electronic equipment and system functions directly depends on the performance of the clock source used. Usually digital systems use off-chip quartz crystal oscillators to obtain clock source signals. Quartz crystal oscillators have superior voltage and temperature characteristics and can work stably, but they are difficult to integrate into the chip and increase the cost of the device, hindering the high integration of the chip change. [0003] At present, the clock frequency obtained from the off-chip crystal oscillator is fixed, and the frequency can only be changed through circuits such as DDS or PLL. Contents of the invention [0004] The object of the present...

Claims

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Application Information

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IPC IPC(8): H03K19/173
Inventor 李洪涛朱晓华洪弘陈诚
Owner 无锡南理工新能源电动车科技发展有限公司
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