Complementary metal oxide semiconductor (CMOS) device with double metal gates and manufacturing method thereof

Abstract

The invention relates to a complementary metal oxide semiconductor (CMOS) device with double metal gates and a manufacturing method thereof. The device comprises a semiconductor substrate, a first type metal oxide semiconductor (MOS) device and a second type MOS device, wherein the first type MOS device comprises a first gate stack; the second type MOS device with an opposite conduction type comprises a second gate stack; and the first type MOS device and the second type MOS device are formed on the substrate. The first gate stack is formed by a first gate insulating layer, a first work function adjusting layer and a first filling metal layer, wherein the first work function adjusting layer is formed on the first gate insulating layer and is applicable to the first type MOS device, and the bottom and the side of the first filling metal layer are enclosed by the first work function adjusting layer. The second gate stack is formed by a second gate insulating layer, a second work function adjusting layer and a second filling metal layer, wherein the second work function adjusting layer is formed on the second gate insulating layer and is applicable to the second type MOS device, and the bottom and the side of the second filling metal layer are enclosed by the second work function adjusting layer.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a CMOS device with double metal gates and a manufacturing method thereof. Background technique [0002] Starting from the 45nm CMOS integrated circuit process, as the feature size of the device continues to shrink, in order to suppress the short channel effect, the effective oxide thickness (EOT) of the gate insulating dielectric layer must be reduced simultaneously. However, the ultra-thin conventional oxide layer or nitride The oxide layer produces severe gate leakage, so the poly-Si / SiON system is no longer applicable. [0003] The interface and internal polarization charges of high-K materials make it difficult to adjust the threshold value of the device. The Fermi level pinning effect produced by the combination of poly-Si and high-K cannot be applied to the threshold value adjustment of MOS devices, so different metal materials must be used for the gate electrode to adjust th...

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Problems solved by technology

[0012] In the above-mentioned conventional process, the step of removing the NMOS work function adjustment layer on the PMOS device is likely to cause damage to the gate insulating layer 105A of the PMOS device

Although an etch stop layer can be added, this will increase the process complexity and weaken the ability of the metal gate to adjust the device threshold

In addition, in the NMOS device, the post-deposited PMOS work function adjustment layer 125 is deposited on the NMOS work function adjustment layer 120, which has a negative impact on the threshold value adjustment of the NMOS device.

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