A low-power multiplier based on bypass technology

Abstract

The invention discloses a low-power consumption multiplying unit based on the Bypass technology, multiplication calculation of two N-digit operands is achieved, and a full adder and a half adder which are based on the gating rank Bypass technology are mainly adopted. The multiplying unit comprises Booth coding logic, Booth decoding logic, a partial product compaction tree based on the Bypass and a fast adder based on the Bypass and the like. According to the Booth coding and decoding logic, an improved Booth coding mode is adopted, and the two N-digit operands are processed to obtain M partial products. The M partial products are processed by the partial product compaction tree, the basic units of the partial product compaction tree are the full adder and the half adder which are based on the rank Bypass, partial summation logic is closed selectively by the Bypass technology through the use of a gating unit, therefore moving switching of transistors is reduced, delay in critical paths is reduced, and thus the design of high performance and low power consumption is achieved.

Description

technical field [0001] The invention belongs to the technical field of multiplication in integrated circuit design, in particular to a low-power multiplier based on Bypass technology. Background technique [0002] The multiplier is an important component in the integrated circuit, which undertakes a large number of calculation tasks and is widely used in the module design of the chip. The multiplier is generally located in the critical path of the chip, and its speed and power consumption have a decisive effect on the performance and power consumption of the entire chip. With the development of chip technology and the advancement of nanoscale technology, performance and power consumption have become the two most important indicators for evaluating chips. The development of technology towards smaller nanoscale has brought a certain improvement to the speed of the chip, but it poses a challenge to the design of low power consumption, and the application of embedded systems pu...

AI Technical Summary

Problems solved by technology

However, these two technologies can only be applied to lower-speed array multipliers. This is because row Bypass and column Bypass technologies can only be used when partial products use array compression and accumulation, which has certain limitations.

Due to the irregularity of the tree structure, row Bypass technology and column Bypass technology cannot be applied to tree multipliers

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