Non-volatile memory unit

Abstract

The invention discloses a non-volatile memory unit. The non-volatile memory unit comprises a coupling device and a first selection transistor. The coupling device is formed in a first conductive area. The first selection transistor is connected in series with a first floating gate transistor and a second selection transistor, wherein the first selection transistor, the first floating gate transistor and the second selection transistor are all formed in a second conductive area. Electrodes of the coupling device and gate electrodes of the first floating gate transistor are integrated floating gate electrodes. The first conductive area and the second conductive area are both formed in a third conductive area, wherein the first conductive area, the second conductive area and the third conductive area are all doped wells. As a result, the non-volatile memory unit is completely compatible with general complementary metal oxide semiconductor processes, only requires a relatively small arrangement area, and demonstrates good write-in and erasing speeds, durability and data memory performance without reducing a circulation speed.

Description

technical field [0001] The present invention relates to a non-volatile storage unit that can be programmed multiple times (multiple time programming, MTP), especially a non-volatile storage unit that is fully compatible with common complementary metal oxide semiconductor manufacturing processes. . Background technique [0002] In the trend of integrating different circuit blocks into a single integrated circuit, the non-volatile memory blocks are also developing towards the integration of logic function blocks. However, many non-volatile memory processes require stacked gate structures, which cannot be integrated into general logic processes. For example, a general semiconductor manufacturing process only needs to use a single polysilicon layer and has no special charge-trapping structure. [0003] US Patent Nos. 7,382,658, 7,391,647, 7,263,001, 7,423,903 and 7,209,392 teach various structures that make up memory cells. US Patent No. 7,382,658 teaches a P-type access tran...

AI Technical Summary

Problems solved by technology

However, many non-volatile memory processes require stacked gate structures and cannot be integrated into general logic processes

For example, the general semiconductor process only needs to use a single polysilicon layer and there is no special charge-trapping structure

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