Semiconductor packaging piece, prefabricated lead frame and manufacturing method thereof

Abstract

The invention provides a semiconductor packaging piece, a prefabricated lead frame and a manufacturing method thereof. The semiconductor packaging piece comprises packaging colloid; a plurality of guide pins partially embedded into the packaging colloid; surface processing layers formed on the top surface, the bottom surface and the recess of each guide pin; and a semiconductor chip embedded in the packaging colloid and used for being electrically connected with the guide pins.

Description

technical field [0001] The invention relates to a semiconductor package and a manufacturing method thereof, in particular to a quad-flat non-leaded (QFN) semiconductor package and a manufacturing method thereof. Background technique [0002] With the rapid development of semiconductor technology, various packaging structures have been developed for semiconductor devices, and the semiconductor device mainly uses a lead frame (Lead Frame) as a chip carrier to form a semiconductor package. The lead frame includes a chip seat and a plurality of leads formed around the chip seat, the semiconductor chip is bonded to the chip seat, and the chip is electrically connected to the plurality of leads with bonding wires, and then covered by encapsulant The chip, the chip seat, the bonding wire and the plurality of leads form the semiconductor package of the lead frame. [0003] In addition, there are many types and types of semiconductor packages with lead frames, for example, quad-flat...

AI Technical Summary

Problems solved by technology

However, when this type of package is formed into the encapsulant, it is easy to overflow the glue and pollute the bottom surface of the lead. After forming the encapsulant, thermal stress will remain in the encapsulant, and after the singulation process, it will cause burrs on the outer edge of the lead. When the distance between the guide pins is too small, it is easy to contact with the adjacent guide pins and cause a short circuit

[0006] On the other hand, Japanese Patent No. 11-251505, Japanese Patent No. 09-312355, Japanese Patent No. 2001-024135, and Japanese Patent No. 2005-317998 have developed a square flat non-guide pin whose guide pin protrudes from the bottom surface of the encapsulant. However, when the package needs to be reworked after soldering the external device, after the package is removed from the printed circuit board, it usually results in poor coplanarity of the leads or plating on the leads shedding problem

Therefore, the package that needs to be reworked cannot be reused after reprocessing

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