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Automatic wiring method of integrated circuit layout after lessening experiment

An integrated circuit and wiring technology, applied in the field of integrated circuit layout processing, can solve the problems of inability to wire, easy to make mistakes, take a long time, etc., to achieve the effect of fast automatic connection and speed up

Active Publication Date: 2013-06-05
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The EDA (Electronic Design Automation) layout and routing tool commonly used in the industry uses a maze algorithm for automatic wiring of the integrated circuit layout after the shrinkage experiment. The wiring effect is very messy, and some areas cannot be wired.
The current common practice is to use manual processing, which takes a long time and is prone to errors

Method used

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  • Automatic wiring method of integrated circuit layout after lessening experiment
  • Automatic wiring method of integrated circuit layout after lessening experiment
  • Automatic wiring method of integrated circuit layout after lessening experiment

Examples

Experimental program
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Embodiment Construction

[0042] The method for automatic connection of the integrated circuit layout of the present invention after the reduction experiment comprises the following steps:

[0043] In the first step, the reduced cell array 10' is simply referred to as the reduced array 10'.

[0044] see Figure 1c , the peripheral circuit 20 is divided into four areas: upper, lower, left and right, which are respectively called the peripheral left area 21 , the peripheral upper area 22 , the peripheral right area 23 , and the peripheral lower area 24 .

[0045] The blank area 30 between the reduced array 10' and the peripheral circuit 20 is also divided into four areas: upper, lower, left and right, which are respectively called blank left area 31, blank upper area 32, blank right area 33, blank lower area 34.

[0046] Preferably, the reduced array 10 ′, the inner and outer rings of the peripheral circuit 20 , and the inner and outer rings of the blank area 30 are all rectangles on the layout, and th...

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Abstract

The invention discloses an automatic wiring method of an integrated circuit layout after a lessening experiment. The total layout is divided into an upper area, a lower area, a left area and a right area. For any one area, two-layer metal wiring is utilized. The metal wiring either comprises transverse wires-vertical wires from top to bottom-transverse wires, or comprises transverse wires-vertical wires from bottom to top-transverse wires. The automatic wiring method can rapidly achieve automatic wiring of the integrated circuit layout after the lessening experiment, original manual wiring needing a long time is shortened to a few minutes, and tape-out verification of integrated circuit chips is speeded up.

Description

technical field [0001] The present invention relates to a method for processing an integrated circuit layout. Background technique [0002] In order to improve competitiveness, the layout of integrated circuits often requires shrinking experiments. For example, the shrinking experiment of the IP core (intellectual property core) mainly shrinks the internal cell array to test whether the function is still normal, which is especially useful when the tape-out test is performed in a short time. [0003] see Figure 1a , which is a layout of an IP core, including a cell array 10 and peripheral circuits 20 located in the central area. see Figure 1b , after the shrinking experiment, an annular blank area 30 is formed between the reduced cell array 10' and the peripheral circuit 20. Originally, there are many connections between the cell array 10 and the peripheral circuit 20 . The connections between the reduced cell array 10' and the peripheral circuits 20 are all disconnecte...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 张兴洲倪凌云孙长江
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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