Automatic wiring method of integrated circuit layout after lessening experiment

An integrated circuit and wiring technology, applied in the field of integrated circuit layout processing, can solve the problems of inability to wire, easy to make mistakes, take a long time, etc., to achieve the effect of fast automatic connection and speed up
CN103136385AActive Publication Date: 2013-06-05SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
Publication Date
2013-06-05

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Abstract

The invention discloses an automatic wiring method of an integrated circuit layout after a lessening experiment. The total layout is divided into an upper area, a lower area, a left area and a right area. For any one area, two-layer metal wiring is utilized. The metal wiring either comprises transverse wires-vertical wires from top to bottom-transverse wires, or comprises transverse wires-vertical wires from bottom to top-transverse wires. The automatic wiring method can rapidly achieve automatic wiring of the integrated circuit layout after the lessening experiment, original manual wiring needing a long time is shortened to a few minutes, and tape-out verification of integrated circuit chips is speeded up.
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Description

technical field

[0001] The present invention relates to a method for processing an integrated circuit layout. Background technique

[0002] In order to improve competitiveness, the layout of integrated circuits often requires shrinking experiments. For example, the shrinking experiment of the IP core (intellectual property core) mainly shrinks the internal cell array to test whether the function is still normal, which is especially useful when the tape-out test is performed in a short time.

[0003] see Figure 1a , which is a layout of an IP core, including a cell array 10 and peripheral circuits 20 located in the central area. see Figure 1b , after the shrinking experiment, an annular blank area 30 is formed between the reduced cell array 10' and the peripheral circuit 20. Originally, there are many connections between the cell array 10 and the peripheral circuit 20 . The connections between the reduced cell array 10' and the peripheral circuits 20 are all disconnecte...

Claims

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