Semiconductor memory cell and manufacturing method thereof
A storage unit and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as difficulty in mass production, affecting the volume and size of storage units, and achieve a reduction in volume and meet read current requirements. Effect
Active Publication Date: 2015-08-19
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology
[0006] However, the above-mentioned three-dimensional FinFET semiconductor storage unit is difficult to mass-produce because its characteristic line width has been reduced to a process node of 20nm or below, and the source and drain of the FinFET storage unit formed according to the above structure are designed to meet the requirements when reading the storage unit. Current, to form a pad for integrated circuit interconnection at the source / drain, and the pad will affect the volume and size of the memory cell
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[0055] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and examples.
[0056] The invention provides a semiconductor storage unit, such as Figure 1a and Figure 1b As shown, it includes STI layers 2a, 2b disposed on the semiconductor substrate 1, and a gate region disposed on the STI layers 2a, 2b, the gate region is composed of two strip gates G1, G2 vertically intersecting;
[0057] Each source / drain region of the four source / drain regions S / D1-S / D4 and its adjacent two source / drain regions are distributed axially symmetrically with the two gates G1 and G2 as symmetrical axes, Specifically, the first source / drain region S / D1 and the second source / drain region S / D2 are arranged axially symmetrically with the first gate G1, and the second source / drain region S / D2 and the third source / drain region The electrode region S / D...
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The invention provides a semiconductor storage unit, a manufacturing method and a storage array. The semiconductor storage unit is formed by a formed cross gate and a sealed strip-shaped active area based on a FinFET structure, wherein the gate is ingeniously contacted with the active area through a charge storage compound layer. The manufacturing method is adaptive to the prior art and can achieve large-scale industrial production. In the semiconductor storage unit, storage position axial symmetrical relative to the gate are in parallel connection to form the storage array to achieve 2-bit storage of all semiconductor units. Thus, a source leakage electrode is not provided with an additional pad, and the size of the storage unit is reduced.
Description
technical field [0001] The invention relates to the field of semiconductor memory, in particular to a semiconductor memory unit and a manufacturing method thereof. Background technique [0002] With the development of semiconductor technology, the feature size of metal oxide semiconductor transistor (MOSFET), which is one of the signs of its development, has been continuously shrinking following Moore's law. In order to meet the miniaturization and high performance requirements of integrated circuits, three-dimensional integration technology has been widely valued in recent years. Taking MOS as an example, three-dimensional structures such as horizontal multi-faceted gate structure and vertical multi-faceted gate structure have been developed. [0003] The three-dimensional multi-plane gate MOSFET can be intuitively divided into horizontal multi-plane gate MOSFET (Planar DG) and vertical multi-plane gate MOSFET according to the parallel or vertical position relationship betw...
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IPC IPC(8): H01L29/78H01L29/423H01L21/336H01L27/115H10B69/00
Inventor 凌龙陈荣堂张传宝邓霖黄军
Owner SEMICON MFG INT (SHANGHAI) CORP