Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device. The manufacturing method of the semiconductor device comprises providing a semiconductor substrate, forming an etching stop layer and an interlayer dielectric layer on the semiconductor substrate from bottom to up in a sequentially stacked mode, and forming copper metal interconnecting wires in the interlayer dielectric layer; forming a silicon layer on the semiconductor substrate; imaging the silicon layer, and etching the silicon layer and the interlayer dielectric layer in sequence to from a groove between the copper metal interconnecting wires; carrying out oxidation treatment on the silicon layer to narrow a top opening of the groove; carrying out ion implantation on the silicon layer which is processed by the oxidation treatment; and forming the interlayer dielectric layer on the semiconductor substrate to completely seal the top opening of the groove. According to the manufacturing method of the semiconductor device, an air gap with a larger feature size can be formed between copper metal interconnecting structures, and therefore the sizes of interconnecting capacitor is effectively reduced. Meanwhile, a k value of the interlayer dielectric layer can be further reduced through an adopted implantation technology.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for forming an air gap. Background technique [0002] As the feature size of semiconductor devices shrinks, the performance of very large scale integration (VLSI) chips is increasingly constrained by interconnect capacitance. In order to reduce the influence of the interconnection capacitance to reduce RC delay and power consumption, it is a very effective solution to integrate a process for forming an air gap in the low-k dielectric layer / copper metal interconnection process. [0003] The traditional process steps for forming an air gap include: first, as Figure 1A As shown, a semiconductor substrate 100 is provided, an interlayer dielectric layer 101 and a low-k dielectric layer 102 are formed from bottom to top on the semiconductor substrate 100, and a first copper metal is formed in the low-k dielectric layer 102 An interconnection structure 103, wherein a c...

AI Technical Summary

Problems solved by technology

[0004] When the above process is used to form the air gap, since the stacked layers of materials form a complex structure, it is difficult to form an air gap with a

Images